.SUBCKT 7400  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_00 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_00 ugate (tplhTY=11ns tplhMX=22ns tphlTY=7ns tphlMX=15ns)
.ENDS  7400


.SUBCKT  74AC00   A0  B0  O0BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 nand(2) DPWR DGND
+  A0  B0  O0BAR
+  DLY_MOD IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 1.5ns     TplhTY= 6.0ns    TplhMX= 8.0ns
+  TphlMN= 1.5ns     TphlTY= 4.5ns    TphlMX= 6.5ns
+  )
.ENDS  74AC00


.SUBCKT  74ACT00   A0  B0  O0BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 nand(2) DPWR DGND
+  A0  B0  O0BAR
+  DLY_MOD IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 1.5ns     TplhTY= 5.5ns    TplhMX= 9.0ns
+  TphlMN= 1.5ns     TphlTY= 4.0ns    TphlMX= 7.0ns
+  )
.ENDS  74ACT00


.SUBCKT 74ALS00 1A 1B 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ 1A 1B 1Y
+ DLY_ALS00 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS00 UGATE (TPLHTY=4NS TPHLTY=3NS)
.ENDS 74ALS00


.SUBCKT 74ALS00A  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ALS00 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS00 ugate (tplhMN=3ns tplhMX=11ns tphlMN=2ns tphlMX=8ns)
.ENDS  74ALS00A


.SUBCKT 74AS00  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_AS00 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS00 ugate (tplhMN=1ns tplhMX=4.5ns tphlMN=1ns tphlMX=4ns)
.ENDS  74AS00


.SUBCKT  74F00   A0  B0  O0BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 nand(2) DPWR DGND
+  A0  B0  O0BAR
+  DLY_MOD IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 2.4ns     TplhTY= 3.7ns    TplhMX= 5.0ns
+  TphlMN= 1.5ns     TphlTY= 3.2ns    TphlMX= 4.3ns
+  )
.ENDS  74F00


.SUBCKT 74H00  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_H00 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H00 ugate (tplhTY=5.9ns tplhMX=10ns tphlTY=6.2ns tphlMX=10ns)
.ENDS  74H00


.SUBCKT 74HC00  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_HC00 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC00 ugate (tplhTY=9ns tplhMX=18ns tphlTY=9ns tphlMX=18ns)
.ENDS  74HC00


.SUBCKT 74HC00A A1 B1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ A1 B1 Y1
+ DLY_HC00A IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HC00A UGATE (TPLHMX=15NS TPHLMX=15NS)
.ENDS 74HC00A


.SUBCKT 74HCT00  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_HCT00 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HCT00 ugate (tplhTY=11ns tplhMX=20ns tphlTY=11ns tphlMX=20ns)
.ENDS  74HCT00


.SUBCKT 74HCT00A A1 B1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ A1 B1 Y1
+ DLY_HCT00A IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT00A UGATE (TPLHMX=19NS TPHLMX=19NS)
.ENDS 74HCT00A


.SUBCKT 74LS00  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS00 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS00 ugate (tplhTY=9ns tplhMX=15ns tphlTY=10ns tphlMX=15ns)
.ENDS  74LS00


.SUBCKT 74S00  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_S00 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S00 ugate (tplhTY=3ns tplhMX=4.5ns tphlTY=3ns tphlMX=5ns)
.ENDS  74S00


.SUBCKT 7401  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_01 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_01 ugate (tplhTY=35ns tplhMX=55ns tphlTY=8ns tphlMX=15ns)
.ENDS  7401


.SUBCKT 74ALS01  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ALS01 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS01 ugate (tplhMN=23ns tplhMX=54ns tphlMN=8ns tphlMX=28ns)
.ENDS  74ALS01


.SUBCKT 74H01  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_H01 IO_H_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H01 ugate (tplhTY=10ns tplhMX=15ns tphlTY=7.5ns tphlMX=12ns)
.ENDS  74H01


.SUBCKT 74HC01  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_HC01 IO_HC_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC01 ugate (tplhTY=13ns tplhMX=25ns tphlTY=10ns tphlMX=20ns)
.ENDS  74HC01


.SUBCKT 74LS01  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS01 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS01 ugate (tplhTY=17ns tplhMX=32ns tphlTY=15ns tphlMX=28ns)
.ENDS  74LS01


.SUBCKT 7402  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_02 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_02 ugate (tplhTY=12ns tplhMX=22ns tphlTY=8ns tphlMX=15ns)
.ENDS  7402


.SUBCKT  74AC02   A0  B0  O0BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 nor(2) DPWR DGND
+  A0  B0  O0BAR
+  DLY_MOD IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 1.5ns     TplhTY= 4.0ns    TplhMX= 6.0ns
+  TphlMN= 1.5ns     TphlTY= 4.5ns    TphlMX= 6.5ns
+  )
.ENDS  74AC02


.SUBCKT 74ACT02  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ACT02 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT02 ugate (tplhMN=1.5ns tplhTY=6.1ns tplhMX=9.4ns tphlMN=1.5ns  
+                               tphlTY=5.3ns tphlMX=7.8ns)
.ENDS  74ACT02


.SUBCKT 74ALS02  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ALS02 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS02 ugate (tplhMN=3ns tplhMX=12ns tphlMN=3ns tphlMX=10ns)
.ENDS  74ALS02


.SUBCKT 74AS02  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_AS02 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS02 ugate (tplhMN=1ns tplhMX=4.5ns tphlMN=1ns tphlMX=4.5ns)
.ENDS  74AS02


.SUBCKT  74F02   A0  B0  O0BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 nor(2) DPWR DGND
+  A0  B0  O0BAR
+  DLY_MOD IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 2.5ns     TplhTY= 4.4ns    TplhMX= 5.5ns
+  TphlMN= 1.5ns     TphlTY= 3.2ns    TphlMX= 4.3ns
+  )
.ENDS  74F02


.SUBCKT 74HC02  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_HC02 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC02 ugate (tplhTY=9ns tplhMX=18ns tphlTY=9ns tphlMX=18ns)
.ENDS  74HC02


.SUBCKT 74HC02A A1 B1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NOR(2) DPWR DGND
+ A1 B1 Y1
+ DLY_HC02A IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HC02A UGATE (TPLHMX=16NS TPHLMX=16NS)
.ENDS 74HC02A


.SUBCKT 74HCT02  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_HCT02 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HCT02 ugate (tplhTY=11ns tplhMX=20ns tphlTY=11ns tphlMX=20ns)
.ENDS  74HCT02


.SUBCKT 74LS02  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS02 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS02 ugate (tplhTY=10ns tplhMX=15ns tphlTY=10ns tphlMX=15ns)
.ENDS  74LS02


.SUBCKT 74S02  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_S02 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S02 ugate (tplhTY=3.5ns tplhMX=5.5ns tphlTY=3.5ns tphlMX=5.5ns)
.ENDS  74S02


.SUBCKT 7403  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_03 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_03 ugate (tplhTY=35ns tplhMX=45ns tphlTY=8ns tphlMX=15ns)
.ENDS  7403


.SUBCKT 74ALS03 1A 1B 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ 1A 1B 1Y
+ DLY_ALS00 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS00 UGATE (TPLHTY=8NS TPHLTY=12NS)
.ENDS 74ALS03


.SUBCKT 74ALS03B  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ALS03 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS03 ugate (tplhMN=20ns tplhMX=50ns tphlMN=3ns tphlMX=13ns)
.ENDS  74ALS03B


.SUBCKT 74HC03  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_HC03 IO_HC_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC03 ugate (tplhTY=13ns tplhMX=25ns tphlTY=10ns tphlMX=20ns)
.ENDS  74HC03


.SUBCKT 74HC03A A1 B1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ A1 B1 Y1
+ DLY_HC03A IO_HC_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HC03A UGATE (TPLHMX=24NS TPHLMX=24NS)
.ENDS 74HC03A


.SUBCKT 74HCT03 1A 1B 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ 1A 1B 1Y
+ DLY_HCT03 IO_HCT_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT03 UGATE (TPLHTY=12NS TPLHMX=24NS TPHLTY=12NS TPHLMX=24NS)
.ENDS 74HCT03


.SUBCKT 74LS03  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS03 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS03 ugate (tplhTY=17ns tplhMX=32ns tphlTY=15ns tphlMX=28ns)
.ENDS  74LS03


.SUBCKT 74S03  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_S03 IO_S_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S03 ugate (tplhMN=2ns tplhTY=5ns tplhMX=7.5ns tphlMN=2ns tphlTY=4.5ns 
+                                  tphlMX=7ns)
.ENDS  74S03


.SUBCKT 7404  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_04 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_04 ugate (tplhTY=12ns tplhMX=22ns tphlTY=8ns tphlMX=15ns)
.ENDS  7404


.SUBCKT  74AC04   A0  O0BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 inv DPWR DGND
+  A0  O0BAR
+  DLY_MOD IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 1.5ns     TplhTY= 4.0ns    TplhMX= 7.0ns
+  TphlMN= 1.5ns     TphlTY= 3.5ns    TphlMX= 6.5ns
+  )
.ENDS  74AC04


.SUBCKT 74ACT04  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_ACT04 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT04 ugate (tplhMN=1.5ns tplhTY=5.3ns tplhMX=9ns tphlMN=1.5ns
+                                 tphlTY=6.4ns tphlMX=8.7ns)
.ENDS  74ACT04


.SUBCKT 74ALS04 1A 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 INV DPWR DGND
+ 1A 1Y
+ DLY_ALS04 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS04 UGATE (TPLHTY=4NS TPHLTY=3NS)
.ENDS 74ALS04


.SUBCKT 74ALS04B  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_ALS04 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS04 ugate (tplhMN=3ns tplhMX=11ns tphlMN=2ns tphlMX=8ns)
.ENDS  74ALS04B


.SUBCKT 74AS04  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_AS04 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS04 ugate (tplhMN=1ns tplhMX=5ns tphlMN=1ns tphlMX=4ns)
.ENDS  74AS04


.SUBCKT  74F04   A0  O0BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 inv DPWR DGND
+  A0  O0BAR
+  DLY_MOD IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 2.4ns     TplhTY= 3.7ns    TplhMX= 5.0ns
+  TphlMN= 1.5ns     TphlTY= 3.2ns    TphlMX= 4.3ns
+  )
.ENDS  74F04


.SUBCKT 74H04  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_H04 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H04 ugate (tplhTY=6ns tplhMX=10ns tphlTY=6.5ns tphlMX=10ns)
.ENDS  74H04


.SUBCKT 74HC04  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_HC04 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC04 ugate (tplhTY=9ns tplhMX=19ns tphlTY=9ns tphlMX=19ns)
.ENDS  74HC04


.SUBCKT 74HC04A A1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 INV DPWR DGND
+ A1 Y1
+ DLY_HC04A IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HC04A UGATE (TPLHMX=15NS TPHLMX=15NS)
.ENDS 74HC04A


.SUBCKT 74HCT04  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_HCT04 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HCT04 ugate (tplhTY=14ns tplhMX=20ns tphlTY=14ns tphlMX=20ns)
.ENDS  74HCT04


.SUBCKT 74HCT04A A1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 INV DPWR DGND
+ A1 Y1
+ DLY_HCT04A IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT04A UGATE (TPLHMX=15NS TPHLMX=17NS)
.ENDS 74HCT04A


.SUBCKT 74LS04  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_LS04 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS04 ugate (tplhTY=9ns tplhMX=15ns tphlTY=10ns tphlMX=15ns)
.ENDS  74LS04


.SUBCKT 74S04  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_S04 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S04 ugate (tplhTY=3ns tplhMX=4.5ns tphlTY=3ns tphlMX=5ns)
.ENDS  74S04


.SUBCKT 7405  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_05 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_05 ugate (tplhTY=40ns tplhMX=55ns tphlTY=8ns tphlMX=15ns)
.ENDS  7405


.SUBCKT 74AC05  A1  Y1
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     A1 Y1
+     DLY_AC05 IO_AC_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AC05 ugate (tplhMN=1.5ns tplhMX=6ns tphlMN=1.5ns tphlMX=6ns)
.ENDS  74AC05


.SUBCKT 74ACT05  A1  Y1
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     A1 Y1
+     DLY_ACT05 IO_ACT_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT05 ugate (tplhMN=1.5ns tplhMX=8.5ns tphlMN=1.5ns tphlMX=8ns)
.ENDS  74ACT05


.SUBCKT 74ALS05 1A 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 INV DPWR DGND
+ 1A 1Y
+ DLY_ALS05 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS05 UGATE (TPLHTY=13NS TPHLTY=8NS)
.ENDS 74ALS05


.SUBCKT 74ALS05A  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_ALS05 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS05 ugate (tplhMN=23ns tplhMX=54ns tphlMN=4ns tphlMX=14ns)
.ENDS  74ALS05A


.SUBCKT 74H05  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_H05 IO_H_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H05 ugate (tplhTY=10ns tplhMX=15ns tphlTY=7.5ns tphlMX=12ns)
.ENDS  74H05


.SUBCKT 74HC05  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_HC05 IO_HC_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC05 ugate (tplhTY=13ns tplhMX=23ns tphlTY=9ns tphlMX=17ns)
.ENDS  74HC05


.SUBCKT 74LS05  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_LS05 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS05 ugate (tplhTY=17ns tplhMX=32ns tphlTY=15ns tphlMX=28ns)
.ENDS  74LS05


.SUBCKT 74S05  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_S05 IO_S_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S05 ugate (tplhMN=2ns tplhTY=5ns tplhMX=7.5ns tphlMN=2ns tphlTY=4.5ns 
+                                 tphlMX=7ns)
.ENDS  74S05


.SUBCKT 7406  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_06 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_06 ugate (tplhTY=10ns tplhMX=15ns tphlTY=15ns tphlMX=23ns)
.ENDS  7406


.SUBCKT 74F06 A0 Y0
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 INV DPWR DGND
+ A0 Y0
+ DLY_F06 IO_F_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_F06 UGATE (TPLHMN=2NS TPLHTY=3.5NS TPLHMX=6NS
+                     TPHLMN=1.5NS TPHLTY=3NS TPHLMX=5.5NS)
.ENDS 74F06


.SUBCKT 74F06A A0 Y0
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 INV DPWR DGND
+ A0 Y0
+ DLY_F06A IO_F_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_F06A UGATE (TPLHMN=5NS TPLHTY=9NS TPLHMX=11NS
+                     TPHLMN=2NS TPHLTY=4NS TPHLMX=6NS)
.ENDS 74F06A


.SUBCKT 7407  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 buf DPWR DGND
+     1A 1Y
+     DLY_07 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_07 ugate (tplhTY=6ns tplhMX=15ns tphlTY=20ns tphlMX=26ns)
.ENDS  7407


.SUBCKT 74F07 A0 Y0
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 BUF DPWR DGND
+ A0 Y0
+ DLY_F07 IO_F_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_F07 UGATE (TPLHMN=2NS TPLHTY=4NS TPLHMX=6NS
+                     TPHLMN=3NS TPHLTY=5NS TPHLMX=7NS)
.ENDS 74F07


.SUBCKT 74F07A A0 Y0
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 BUF DPWR DGND
+ A0 Y0
+ DLY_F07 IO_F_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_F07 UGATE (TPLHMN=6NS TPLHTY=10.5NS TPLHMX=13NS
+                     TPHLMN=5NS TPHLTY=7.5NS TPHLMX=10NS)
.ENDS 74F07A


.SUBCKT 74LS07  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 buf DPWR DGND
+     1A 1Y
+     DLY_LS07 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS07 ugate (tplhTY=6ns tplhMX=10ns tphlTY=19ns tphlMX=30ns)
.ENDS  74LS07


.SUBCKT 7408  1A 1B  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+     1A 1B 1Y
+     DLY_08 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_08 ugate (tplhTY=17.5ns tplhMX=27ns tphlTY=12ns tphlMX=19ns)
.ENDS  7408


.SUBCKT  74AC08   A0  B0  O0
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 and(2) DPWR DGND
+  A0  B0  O0
+  DLY_MOD IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 1.5ns     TplhTY= 5.5ns    TplhMX= 7.5ns
+  TphlMN= 1.5ns     TphlTY= 5.5ns    TphlMX= 7.0ns
+  )
.ENDS  74AC08


.SUBCKT 74ACT08  1A 1B  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ACT08 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT08 ugate (tplhMN=1.5ns tplhTY=5.8ns tplhMX=8ns tphlMN=1.5ns
+                                    tphlTY=5.2ns tphlMX=7.7ns)
.ENDS  74ACT08


.SUBCKT 74ALS08  1A 1B  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ALS08 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS08 ugate (tplhMN=4ns tplhMX=14ns tphlMN=3ns tphlMX=10ns)
.ENDS  74ALS08


.SUBCKT 74AS08  1A 1B  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+     1A 1B 1Y
+     DLY_AS08 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS08 ugate (tplhMN=1ns tplhMX=5.5ns tphlMN=1ns tphlMX=5.5ns)
.ENDS  74AS08


.SUBCKT  74F08   A0  B0  O0
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 and(2) DPWR DGND
+  A0  B0  O0
+  DLY_MOD IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 3.0ns     TplhTY= 4.2ns    TplhMX= 5.6ns
+  TphlMN= 2.5ns     TphlTY= 4.0ns    TphlMX= 5.3ns
+  )
.ENDS  74F08


.SUBCKT 74HC08  1A 1B  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+     1A 1B 1Y
+     DLY_HC08 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC08 ugate (tplhTY=10ns tplhMX=20ns tphlTY=10ns tphlMX=20ns)
.ENDS  74HC08


.SUBCKT 74HC08A A1 B1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 AND(2) DPWR DGND
+ A1 B1 Y1
+ DLY_HC08A IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HC08A UGATE (TPLHMX=15NS TPHLMX=15NS)
.ENDS 74HC08A


.SUBCKT 74HCT08  1A 1B  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+     1A 1B 1Y
+     DLY_HCT08 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HCT08 ugate (tplhTY=15ns tplhMX=24ns tphlTY=15ns tphlMX=24ns)
.ENDS  74HCT08


.SUBCKT 74HCT08A A1 B1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 AND(2) DPWR DGND
+ A1 B1 Y1
+ DLY_HCT08A IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT08A UGATE (TPLHMX=19NS TPHLMX=19NS)
.ENDS 74HCT08A


.SUBCKT 74LS08  1A 1B  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS08 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS08 ugate (tplhTY=8ns tplhMX=15ns tphlTY=10ns tphlMX=20ns)
.ENDS  74LS08


.SUBCKT 74S08  1A 1B  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+     1A 1B 1Y
+     DLY_S08 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S08 ugate (tplhTY=4.5ns tplhMX=7ns tphlTY=5ns tphlMX=7.5ns)
.ENDS  74S08


.SUBCKT 7409  1A 1B  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+     1A 1B 1Y
+     DLY_09 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_09 ugate (tplhTY=21ns tplhMX=32ns tphlTY=16ns tphlMX=24ns)
.ENDS  7409


.SUBCKT 74ALS09  1A 1B  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ALS09 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS09 ugate (tplhMN=23ns tplhMX=54ns tphlMN=5ns tphlMX=15ns)
.ENDS  74ALS09


.SUBCKT 74HC09  1A 1B  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+     1A 1B 1Y
+     DLY_HC09 IO_HC_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC09 ugate (tplhTY=13ns tplhMX=25ns tphlTY=10ns tphlMX=20ns)
.ENDS  74HC09


.SUBCKT 74LS09  1A 1B  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS09 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS09 ugate (tplhTY=20ns tplhMX=35ns tphlTY=17ns tphlMX=35ns)
.ENDS  74LS09


.SUBCKT 74S09  1A 1B  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(2) DPWR DGND
+     1A 1B 1Y
+     DLY_S09 IO_S_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S09 ugate (tplhTY=6.5ns tplhMX=10ns tphlTY=6.5ns tphlMX=10ns)
.ENDS  74S09


.SUBCKT 7410  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_10 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_10 ugate (tplhTY=11ns tplhMX=22ns tphlTY=7ns tphlMX=15ns)
.ENDS  7410


.SUBCKT  74AC10   A0  B0  C0  O0BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 nand(3) DPWR DGND
+  A0  B0  C0  O0BAR
+  DLY_MOD IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 1.5ns     TplhTY= 4.5ns    TplhMX= 7.0ns
+  TphlMN= 1.5ns     TphlTY= 4.0ns    TphlMX= 6.0ns
+  )
.ENDS  74AC10


.SUBCKT 74ACT10  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_ACT10 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT10 ugate (tplhMN=1.5ns tplhTY=5.8ns tplhMX=8.2ns tphlMN=1.5ns
+                                 tphlTY=5.7ns tphlMX=7.4ns)
.ENDS  74ACT10


.SUBCKT 74ALS10 1A 1B 1C 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(3) DPWR DGND
+ 1A 1B 1C 1Y
+ DLY_ALS10 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS10 UGATE (TPLHTY=4NS TPHLTY=10NS)
.ENDS 74ALS10


.SUBCKT 74ALS10A  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_ALS10 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS10 ugate (tplhMN=2ns tplhMX=11ns tphlMN=2ns tphlMX=10ns)
.ENDS  74ALS10A


.SUBCKT 74AS10  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_AS10 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS10 ugate (tplhMN=1ns tplhMX=4.5ns tphlMN=1ns tphlMX=4.5ns)
.ENDS  74AS10


.SUBCKT  74F10   A0  B0  C0  O0BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 nand(3) DPWR DGND
+  A0  B0  C0  O0BAR
+  DLY_MOD IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 2.4ns     TplhTY= 3.7ns    TplhMX= 5.0ns
+  TphlMN= 1.5ns     TphlTY= 3.2ns    TphlMX= 4.3ns
+  )
.ENDS  74F10


.SUBCKT 74H10  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_H10 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H10 ugate (tplhTY=5.9ns tplhMX=10ns tphlTY=6.3ns tphlMX=10ns)
.ENDS  74H10


.SUBCKT 74HC10  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_HC10 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC10 ugate (tplhTY=10ns tplhMX=19ns tphlTY=10ns tphlMX=19ns)
.ENDS  74HC10


.SUBCKT 74HCT10 1A 1B 1C 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(3) DPWR DGND
+ 1A 1B 1C 1Y
+ DLY_HCT10 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT10 UGATE (TPLHTY=14NS TPLHMX=24NS TPHLTY=14NS TPHLMX=24NS )
.ENDS 74HCT10


.SUBCKT 74LS10  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_LS10 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS10 ugate (tplhTY=9ns tplhMX=15ns tphlTY=10ns tphlMX=15ns)
.ENDS  74LS10


.SUBCKT 74S10  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_S10 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S10 ugate (tplhTY=3ns tplhMX=4.5ns tphlTY=3ns tphlMX=5ns)
.ENDS  74S10


.SUBCKT 7411 A B C O
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 AND(3) DPWR DGND
+ A B C O
+ DLY_11 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_11 UGATE (TPLHMX=27NS TPHLMX=19NS)
.ENDS 7411


.SUBCKT  74AC11   A0  B0  C0  O0
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 and(3) DPWR DGND
+  A0  B0  C0  O0
+  DLY_MOD IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 1.5ns     TplhTY= 4.0ns    TplhMX= 8.0ns
+  TphlMN= 1.5ns     TphlTY= 4.0ns    TphlMX= 7.0ns
+  )
.ENDS  74AC11


.SUBCKT 74ACT11  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_ACT11 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT11 ugate (tplhMN=1.5ns tplhTY=6.5ns tplhMX=8.6ns tphlMN=1.5ns
+                                   tphlTY=5.5ns tphlMX=7.9ns)
.ENDS  74ACT11


.SUBCKT 74ALS11 1A 1B 1C 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 AND(3) DPWR DGND
+ 1A 1B 1C 1Y
+ DLY_ALS11 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS11 UGATE (TPLHTY=12NS TPHLTY=6NS)
.ENDS 74ALS11


.SUBCKT 74ALS11A  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_ALS11 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS11 ugate (tplhMN=2ns tplhMX=13ns tphlMN=2ns tphlMX=10ns)
.ENDS  74ALS11A


.SUBCKT 74AS11  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_AS11 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS11 ugate (tplhMN=1ns tplhMX=6ns tphlMN=1ns tphlMX=5.5ns)
.ENDS  74AS11


.SUBCKT  74F11   A0  B0  C0  O0
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 and(3) DPWR DGND
+  A0  B0  C0  O0
+  DLY_MOD IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 3.0ns     TplhTY= 4.2ns    TplhMX= 5.6ns
+  TphlMN= 2.5ns     TphlTY= 4.1ns    TphlMX= 5.5ns
+  )
.ENDS  74F11


.SUBCKT 74H11  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_H11 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H11 ugate (tplhTY=7.6ns tplhMX=12ns tphlTY=8.8ns tphlMX=12ns)
.ENDS  74H11


.SUBCKT 74HC11  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_HC11 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC11 ugate (tplhTY=10ns tplhMX=20ns tphlTY=10ns tphlMX=20ns)
.ENDS  74HC11


.SUBCKT 74HCT11 1A 1B 1C 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 AND(3) DPWR DGND
+ 1A 1B 1C 1Y
+ DLY_HCT11 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT11 UGATE (TPLHTY=16NS TPLHMX=24NS TPHLTY=16NS TPHLMX=24NS )
.ENDS 74HCT11


.SUBCKT 74LS11  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_LS11 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS11 ugate (tplhTY=8ns tplhMX=15ns tphlTY=10ns tphlMX=20ns)
.ENDS  74LS11


.SUBCKT 74S11  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_S11 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S11 ugate (tplhTY=4.5ns tplhMX=7ns tphlTY=5ns tphlMX=7.5ns)
.ENDS  74S11


.SUBCKT 7412  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_12 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_12 ugate (tplhTY=35ns tplhMX=45ns tphlTY=8ns tphlMX=15ns)
.ENDS  7412


.SUBCKT 74ALS12 1A 1B 1C 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(3) DPWR DGND
+ 1A 1B 1C 1Y
+ DLY_ALS12 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS12 UGATE (TPLHTY=14NS TPHLTY=14NS)
.ENDS 74ALS12


.SUBCKT 74ALS12A  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_ALS12 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS12 ugate (tplhMN=23ns tplhMX=54ns tphlMN=5ns tphlMX=18ns)
.ENDS  74ALS12A


.SUBCKT 74LS12  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_LS12 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS12 ugate (tplhTY=17ns tplhMX=32ns tphlTY=15ns tphlMX=28ns)
.ENDS  74LS12


.SUBCKT 7413  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_13 IO_STD_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_13 ugate (tplhTY=18ns tplhMX=27ns tphlTY=15ns tphlMX=22ns)
.ENDS  7413


.SUBCKT 74ALS13 A1 B1 C1 D1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(4) DPWR DGND
+ A1 B1 C1 D1 Y1
+ DLY_ALS13 IO_ALS00_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS13 UGATE (TPLHMN=2NS TPLHMX=12NS TPHLMN=2NS TPHLMX=12NS)
.ENDS 74ALS13


.SUBCKT 74F13 A0 B0 C0 D0 O0BAR
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(4) DPWR DGND
+ A0 B0 C0 D0
+ O0BAR
+ DLY_F13 IO_F_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_F13 UGATE (TPLHMN=5NS TPLHTY=-1 TPLHMX=10.5NS
+                     TPHLMN=9.5NS TPHLTY=-1 TPHLMX=17.5NS)
.ENDS 74F13


.SUBCKT 74LS13  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_LS13 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS13 ugate (tplhTY=15ns tplhMX=22ns tphlTY=18ns tphlMX=27ns)
.ENDS  74LS13


.SUBCKT 7414  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A  1Y
+     DLY_14 IO_STD_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_14 ugate (tplhTY=15ns tplhMX=22ns tphlTY=15ns tphlMX=22ns)
.ENDS  7414


.SUBCKT  74AC14   I0  O0BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 inv DPWR DGND
+  I0  O0BAR
+  DLY_MOD IO_AC_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 1.5ns     TplhTY= 7.0ns    TplhMX= 10.0ns
+  TphlMN= 1.5ns     TphlTY= 6.0ns    TphlMX= 8.5ns
+  )
.ENDS  74AC14


.SUBCKT 74ACT14  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A  1Y
+     DLY_ACT14 IO_ACT_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT14 ugate (tplhMN=2.3ns tplhTY=5.6ns tplhMX=8.4ns tphlMN=3.3ns
+                                  tphlTY=6.4ns tphlMX=8.3ns)
.ENDS  74ACT14


.SUBCKT 74ALS14 A1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 INV DPWR DGND
+ A1 Y1
+ DLY_ALS14 IO_ALS00_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS14 UGATE (TPLHMN=2NS TPLHMX=12NS TPHLMN=2NS TPHLMX=10NS)
.ENDS 74ALS14


.SUBCKT 74F14 I0 O0BAR
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 INV DPWR DGND
+ I0
+ O0BAR
+ DLY_F14 IO_F_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_F14 UGATE (TPLHMN=4NS TPLHTY=-1 TPLHMX=10.5NS
+                     TPHLMN=3.5NS TPHLTY=-1 TPHLMX=8.5NS)
.ENDS 74F14


.SUBCKT 74HC14  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A  1Y
+     DLY_HC14 IO_HC_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC14 ugate (tplhTY=12ns tplhMX=25ns tphlTY=12ns tphlMX=25ns)
.ENDS  74HC14


.SUBCKT 74HC14A A1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 INV DPWR DGND
+ A1 Y1
+ DLY_HC14A IO_HC_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HC14A UGATE (TPLHMX=19NS TPHLMX=19NS)
.ENDS 74HC14A


.SUBCKT 74HCT14 1A 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 INV DPWR DGND
+ 1A 1Y
+ DLY_HCT14 IO_HCT_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT14 UGATE (TPLHTY=20NS TPLHMX=34NS TPHLTY=20NS TPHLMX=34NS)
.ENDS 74HCT14


.SUBCKT 74HCT14A A1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 INV DPWR DGND
+ A1 Y1
+ DLY_HCT14A IO_HCT_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT14A UGATE (TPLHMX=32NS TPHLMX=32NS)
.ENDS 74HCT14A


.SUBCKT 74LS14  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A  1Y
+     DLY_LS14 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS14 ugate (tplhTY=15ns tplhMX=22ns tphlTY=15ns tphlMX=22ns)
.ENDS  74LS14


.SUBCKT 74ALS15 1A 1B 1C 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 AND(3) DPWR DGND
+ 1A 1B 1C 1Y
+ DLY_ALS15 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS15 UGATE (TPLHTY=15NS TPHLTY=15NS)
.ENDS 74ALS15


.SUBCKT 74ALS15A  1A 1B 1C  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(3) DPWR DGND
+     1A 1B 1C  1Y
+     DLY_ALS15 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS15 ugate (tplhMN=20ns tplhMX=45ns tphlMN=6ns tphlMX=20ns)
.ENDS  74ALS15A


.SUBCKT 74H15  1A 1B 1C  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(3) DPWR DGND
+     1A 1B 1C  1Y
+     DLY_H15 IO_H_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H15 ugate (tplhTY=12ns tplhMX=18ns tphlTY=9ns tphlMX=13ns)
.ENDS  74H15


.SUBCKT 74LS15  1A 1B 1C  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(3) DPWR DGND
+     1A 1B 1C  1Y
+     DLY_LS15 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS15 ugate (tplhTY=20ns tplhMX=35ns tphlTY=17ns tphlMX=35ns)
.ENDS  74LS15


.SUBCKT 74S15  1A 1B 1C  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(3) DPWR DGND
+     1A 1B 1C  1Y
+     DLY_S15 IO_S_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S15 ugate (tplhTY=5.5ns tplhMX=8.5ns tphlTY=6ns tphlMX=9ns)
.ENDS  74S15


.SUBCKT 7416  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_16 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_16 ugate (tplhTY=10ns tplhMX=15ns tphlTY=15ns tphlMX=23ns)
.ENDS  7416


.SUBCKT 7417  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 buf DPWR DGND
+     1A 1Y
+     DLY_17 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_17 ugate (tplhTY=6ns tplhMX=15ns tphlTY=20ns tphlMX=26ns)
.ENDS  7417


.SUBCKT 74LS17  1A  1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 buf DPWR DGND
+     1A 1Y
+     DLY_LS17 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS17 ugate (tplhTY=6ns tplhMX=10ns tphlTY=19ns tphlMX=30ns)
.ENDS  74LS17


.SUBCKT 74LS18  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_LS18 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS18 ugate (tplhTY=13ns tplhMX=20ns tphlTY=37ns tphlMX=55ns)
.ENDS  74LS18


.SUBCKT 74LS19A  1A 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_LS19 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS19 ugate (tplhTY=13ns tplhMX=20ns tphlTY=18ns tphlMX=30ns)
.ENDS  74LS19A


.SUBCKT 7420  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_20 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_20 ugate (tplhTY=12ns tplhMX=22ns tphlTY=8ns tphlMX=15ns)
.ENDS  7420


.SUBCKT  74AC20   A0  B0  C0  D0  O0BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 nand(4) DPWR DGND
+  A0  B0  C0  D0  O0BAR
+  DLY_MOD IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 1.5ns     TplhTY= 5.0ns    TplhMX= 7.0ns
+  TphlMN= 1.5ns     TphlTY= 4.0ns    TphlMX= 6.0ns
+  )
.ENDS  74AC20


.SUBCKT 74ACT20  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_ACT20 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT20 ugate (tplhMN=1.5ns tplhTY=5.6ns tplhMX=8.5ns tphlMN=1.5ns
+                                 tphlTY=6.1ns tphlMX=8.4ns)
.ENDS  74ACT20


.SUBCKT 74ALS20 1A 1B 1C 1D 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(4) DPWR DGND
+ 1A 1B 1C 1D 1Y
+ DLY_ALS20 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS20 UGATE (TPLHTY=4NS TPHLTY=4NS)
.ENDS 74ALS20


.SUBCKT 74ALS20A  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_ALS20 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS20 ugate (tplhMN=3ns tplhMX=11ns tphlMN=3ns tphlMX=10ns)
.ENDS  74ALS20A


.SUBCKT 74AS20  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_AS20 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS20 ugate (tplhMN=1ns tplhMX=5ns tphlMN=1ns tphlMX=4.5ns)
.ENDS  74AS20


.SUBCKT  74F20   A0  B0  C0  D0  O0BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 nand(4) DPWR DGND
+  A0  B0  C0  D0  O0BAR
+  DLY_MOD IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 2.4ns     TplhTY= 3.7ns    TplhMX= 5.0ns
+  TphlMN= 1.5ns     TphlTY= 3.2ns    TphlMX= 4.3ns
+  )
.ENDS  74F20


.SUBCKT 74H20  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_H20 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H20 ugate (tplhTY=6ns tplhMX=10ns tphlTY=7ns tphlMX=10ns)
.ENDS  74H20


.SUBCKT 74HC20  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_HC20 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC20 ugate (tplhTY=14ns tplhMX=22ns tphlTY=14ns tphlMX=22ns)
.ENDS  74HC20


.SUBCKT 74HCT20 1A 1B 1C 1D 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(4) DPWR DGND
+ 1A 1B 1C 1D 1Y
+ DLY_HCT20 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT20 UGATE (TPLHTY=16NS TPLHMX=28NS TPHLTY=16NS TPHLMX=28NS)
.ENDS 74HCT20


.SUBCKT 74LS20  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_LS20 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS20 ugate (tplhTY=9ns tplhMX=15ns tphlTY=10ns tphlMX=15ns)
.ENDS  74LS20


.SUBCKT 74S20  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_S20 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S20 ugate (tplhTY=3ns tplhMX=4.5ns tphlTY=3ns tphlMX=5ns)
.ENDS  74S20


.SUBCKT 74AC21  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_AC21 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AC21 ugate (tplhMN=1.5ns tplhTY=5.6ns tplhMX=7.8ns tphlMN=1.5ns
+                                tphlTY=4.6ns tphlMX=6.5ns)
.ENDS  74AC21


.SUBCKT 74ACT21  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_ACT21 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT21 ugate (tplhMN=1.5ns tplhTY=6.7ns tplhMX=8.8ns tphlMN=1.5ns
+                                tphlTY=5.4ns tphlMX=8.3ns)
.ENDS  74ACT21


.SUBCKT 74ALS21 1A 1B 1C 1D 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 AND(4) DPWR DGND
+ 1A 1B 1C 1D 1Y
+ DLY_ALS21 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS21 UGATE (TPLHTY=12NS TPHLTY=5NS)
.ENDS 74ALS21


.SUBCKT 74ALS21A  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_ALS21 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS21 ugate (tplhMN=4ns tplhMX=15ns tphlMN=2ns tphlMX=10ns)
.ENDS  74ALS21A


.SUBCKT 74AS21  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_AS21 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS21 ugate (tplhMN=1ns tplhMX=6ns tphlMN=1ns tphlMX=6ns)
.ENDS  74AS21


.SUBCKT 74F21  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_F21 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_F21 ugate (tplhMN=1ns tplhTY=3.2ns tplhMX=4.7ns
+                               tphlMN=1.5ns tphlTY=3.4ns tphlMX=5.1ns)
.ENDS  74F21


.SUBCKT 74H21  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_H21 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H21 ugate (tplhTY=7.6ns tplhMX=12ns tphlTY=8.8ns tphlMX=12ns)
.ENDS  74H21


.SUBCKT 74HC21  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_HC21 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC21 ugate (tplhTY=14ns tplhMX=22ns tphlTY=14ns tphlMX=22ns)
.ENDS  74HC21


.SUBCKT 74HCT21 1A 1B 1C 1D 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 AND(4) DPWR DGND
+ 1A 1B 1C 1D 1Y
+ DLY_HCT21 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT21 UGATE (TPLHTY=15NS TPLHMX=27NS TPHLTY=15NS TPHLMX=27NS)
.ENDS 74HCT21


.SUBCKT 74LS21  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 and(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_LS21 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS21 ugate (tplhTY=8ns tplhMX=15ns tphlTY=10ns tphlMX=20ns)
.ENDS  74LS21


.SUBCKT 7422  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_22 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_22 ugate (tplhTY=35ns tplhMX=45ns tphlTY=8ns tphlMX=15ns)
.ENDS  7422


.SUBCKT 74ALS22 1A 1B 1C 1D 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(4) DPWR DGND
+ 1A 1B 1C 1D 1Y
+ DLY_ALS22 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS22 UGATE (TPLHTY=14NS TPHLTY=11NS)
.ENDS 74ALS22


.SUBCKT 74ALS22B  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_ALS22 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS22 ugate (tplhMN=23ns tplhMX=45ns tphlMN=4ns tphlMX=18ns)
.ENDS  74ALS22B


.SUBCKT 74H22  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_H22 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H22 ugate (tplhTY=10ns tplhMX=15ns tphlTY=7.5ns tphlMX=12ns)
.ENDS  74H22


.SUBCKT 74LS22  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_LS22 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS22 ugate (tplhTY=17ns tplhMX=32ns tphlTY=15ns tphlMX=28ns)
.ENDS  74LS22


.SUBCKT 74S22  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_S22 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S22 ugate (tplhMN=2ns tplhTY=5ns tplhMX=7.5ns tphlMN=2ns tphlTY=4.5ns 
+                                 tphlMX=7ns)
.ENDS  74S22


.SUBCKT 7423  1G 1A 1B 1C 1D 1X 1XBAR 2G 2A 2B 2C 2D 1Y 2Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1XBAR 1XB
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 aoi(2,5) DPWR DGND
+     1A 1G
+     1B 1G
+     1C 1G
+     1D 1G
+     1X 1XB
+     1Y
+     DLY_23 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 aoi(2,4) DPWR DGND
+     2A 2G
+     2B 2G
+     2C 2G
+     2D 2G
+     2Y
+     DLY_23 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_23 ugate (tplhTY=13ns tplhMX=22ns tphlTY=8ns tphlMX=15ns)
.ENDS  7423


.SUBCKT 74LS24  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS24 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS24 ugate (tplhTY=13ns tplhMX=20ns tphlTY=25ns tphlMX=40ns)
.ENDS  74LS24


.SUBCKT 7425  1G 1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 aoi(2,4) DPWR DGND
+     1A 1G
+     1B 1G
+     1C 1G
+     1D 1G
+     1Y
+     DLY_25 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_25 ugate (tplhTY=13ns tplhMX=22ns tphlTY=8ns tphlMX=15ns)
.ENDS  7425


.SUBCKT 7426  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_26 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_26 ugate (tplhTY=16ns tplhMX=24ns tphlTY=11ns tphlMX=17ns)
.ENDS  7426


.SUBCKT 74LS26  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS26 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS26 ugate (tplhTY=17ns tplhMX=32ns tphlTY=15ns tphlMX=28ns)
.ENDS  74LS26


.SUBCKT 7427  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_27 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_27 ugate (tplhTY=10ns tplhMX=15ns tphlTY=7ns tphlMX=11ns)
.ENDS  7427


.SUBCKT 74AC27  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_AC27 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AC27 ugate (tplhMN=1.5ns tplhTY=4.3ns tplhMX=6.8ns tphlMN=1.5ns 
+                                  tphlTY=4.5ns tphlMX=7.5ns)
.ENDS  74AC27


.SUBCKT 74ACT27  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_ACT27 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT27 ugate (tplhMN=1.5ns tplhTY=5ns tplhMX=9.2ns tphlMN=1.5ns 
+                                  tphlTY=6ns tphlMX=8.6ns)
.ENDS  74ACT27


.SUBCKT 74ALS27  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_ALS27 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS27 ugate (tplhMN=4ns tplhMX=15ns tphlMN=3ns tphlMX=9ns)
.ENDS  74ALS27


.SUBCKT 74AS27  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_AS27 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS27 ugate (tplhMN=1ns tplhMX=5.5ns tphlMN=1ns tphlMX=4.5ns)
.ENDS  74AS27


.SUBCKT  74F27   A1  B1  C1  O1BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 nor(3) DPWR DGND
+  A1  B1  C1  O1BAR
+  DLY_MOD IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 2.0ns     TplhTY= 3.8ns    TplhMX= 6.0ns
+  TphlMN= 1.0ns     TphlTY= 2.6ns    TphlMX= 4.0ns
+  )
.ENDS  74F27


.SUBCKT 74HC27  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_HC27 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC27 ugate (tplhTY=10ns tplhMX=18ns tphlTY=10ns tphlMX=18ns)
.ENDS  74HC27


.SUBCKT 74HCT27 1A 1B 1C 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NOR(3) DPWR DGND
+ 1A 1B 1C 1Y
+ DLY_HCT27 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT27 UGATE (TPLHTY=12NS TPLHMX=21NS TPHLTY=12NS TPHLMX=21NS)
.ENDS 74HCT27


.SUBCKT 74LS27  1A 1B 1C 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(3) DPWR DGND
+     1A 1B 1C 1Y
+     DLY_LS27 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS27 ugate (tplhTY=10ns tplhMX=15ns tphlTY=10ns tphlMX=15ns)
.ENDS  74LS27


.SUBCKT 7428  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_28 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_28 ugate (tplhTY=6ns tplhMX=9ns tphlTY=8ns tphlMX=12ns)
.ENDS  7428


.SUBCKT 74ALS28A  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ALS28 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS28 ugate (tplhMN=2ns tplhMX=8ns tphlMN=2ns tphlMX=7ns)
.ENDS  74ALS28A


.SUBCKT 74LS28  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS28 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS28 ugate (tplhTY=12ns tplhMX=24ns tphlTY=12ns tphlMX=24ns)
.ENDS  74LS28


.SUBCKT 7430  A B C D E F G H Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(8) DPWR DGND
+     A B C D E F G H Y
+     DLY_30 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_30 ugate (tplhTY=13ns tplhMX=22ns tphlTY=8ns tphlMX=15ns)
.ENDS  7430


.SUBCKT 74AC30  A B C D E F G H Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(8) DPWR DGND
+     A B C D E F G H Y
+     DLY_AC30 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AC30 ugate (tplhMN=1.5ns tplhTY=4.8ns tplhMX=6.7ns tphlMN=1.5ns 
+                                tphlTY=4.8ns tphlMX=6.7ns)
.ENDS  74AC30


.SUBCKT 74ACT30  A B C D E F G H Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(8) DPWR DGND
+     A B C D E F G H Y
+     DLY_ACT30 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT30 ugate (tplhMN=1.5ns tplhTY=5.4ns tplhMX=8.1ns tphlMN=1.5ns 
+                                tphlTY=5.9ns tphlMX=7.8ns)
.ENDS  74ACT30


.SUBCKT 74ALS30A  A B C D E F G H Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(8) DPWR DGND
+     A B C D E F G H Y
+     DLY_ALS30 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS30 ugate (tplhMN=3ns tplhMX=10ns tphlMN=3ns tphlMX=12ns)
.ENDS  74ALS30A


.SUBCKT 74AS30  A B C D E F G H Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(8) DPWR DGND
+     A B C D E F G H Y
+     DLY_AS30 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS30 ugate (tplhMN=1ns tplhMX=5ns tphlMN=1ns tphlMX=4.5ns)
.ENDS  74AS30


.SUBCKT  74F30   A0  A1  A2  A3  A4  A5  A6  A7  OBAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 nand(8) DPWR DGND
+  A0  A1  A2  A3  A4  A5  A6  A7  OBAR
+  DLY_MOD IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 1.0ns     TplhTY= 3.7ns    TplhMX= 5.0ns
+  TphlMN= 1.5ns     TphlTY= 2.8ns    TphlMX= 5.0ns
+  )
.ENDS  74F30


.SUBCKT 74H30  A B C D E F G H Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(8) DPWR DGND
+     A B C D E F G H Y
+     DLY_H30 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H30 ugate (tplhTY=6.8ns tplhMX=10ns tphlTY=8.9ns tphlMX=12ns)
.ENDS  74H30


.SUBCKT 74HC30  A B C D E F G H Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(8) DPWR DGND
+     A B C D E F G H Y
+     DLY_HC30 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC30 ugate (tplhTY=15ns tplhMX=26ns tphlTY=15ns tphlMX=26ns)
.ENDS  74HC30


.SUBCKT 74HCT30 A B C D E F G H Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(8) DPWR DGND
+ A B C D E F G H Y
+ DLY_HCT30 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT30 UGATE (TPLHTY=16NS TPLHMX=28NS TPHLTY=16NS TPHLMX=28NS)
.ENDS 74HCT30


.SUBCKT 74LS30  A B C D E F G H Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(8) DPWR DGND
+     A B C D E F G H Y
+     DLY_LS30 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS30 ugate (tplhTY=8ns tplhMX=15ns tphlTY=13ns tphlMX=20ns)
.ENDS  74LS30


.SUBCKT 74S30  A B C D E F G H Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(8) DPWR DGND
+     A B C D E F G H Y
+     DLY_S30 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S30 ugate (tplhTY=4ns tplhMX=6ns tphlTY=4.5ns tphlMX=7ns)
.ENDS  74S30


.SUBCKT 74LS31  1A 2A 3A 3B 1Y 2Y 3Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1A 1Y
+     DLY_31I  IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 buf DPWR DGND
+     2A 2Y
+     DLY_31B  IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 nand(2) DPWR DGND
+     3A 3B 3Y
+     DLY_31N  IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_31I ugate (tplhMN=22ns tplhTY=32ns tplhMX=65ns tphlMN=13ns tphlTY=23ns
+	                     tphlMX=45ns)
.model DLY_31B ugate (tplhMN=31ns tplhTY=45ns tplhMX=80ns tphlMN=30ns tphlTY=48ns
+                                 tphlMX=95ns)
.model DLY_31N ugate (tplhMN=2ns tplhTY=6ns tplhMX=15ns tphlMN=2ns tphlTY=6ns 	
+                                 tphlMX=15ns)
.ENDS  74LS31


.SUBCKT 7432  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 or(2) DPWR DGND
+     1A 1B 1Y
+     DLY_32 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_32 ugate (tplhTY=10ns tplhMX=15ns tphlTY=14ns tphlMX=22ns)
.ENDS  7432


.SUBCKT  74AC32   A0  B0  O0
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 or(2) DPWR DGND
+  A0  B0  O0
+  DLY_MOD IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 1.5ns     TplhTY= 5.5ns    TplhMX= 7.5ns
+  TphlMN= 1.5ns     TphlTY= 5.0ns    TphlMX= 7.0ns
+  )
.ENDS  74AC32


.SUBCKT 74ACT32  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 or(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ACT32 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT32 ugate (tplhMN=1.5ns tplhTY=6.2ns tplhMX=8.1ns tphlMN=1.5ns 
+                                   tphlTY=4.9ns tphlMX=7.4ns)
.ENDS  74ACT32


.SUBCKT 74ALS32  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 or(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ALS32 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS32 ugate (tplhMN=3ns tplhMX=14ns tphlMN=3ns tphlMX=12ns)
.ENDS  74ALS32


.SUBCKT 74AS32  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 or(2) DPWR DGND
+     1A 1B 1Y
+     DLY_AS32 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS32 ugate (tplhMN=1ns tplhMX=5.8ns tphlMN=1ns tphlMX=5.8ns)
.ENDS  74AS32


.SUBCKT  74F32   A0  B0  O0
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 or(2) DPWR DGND
+  A0  B0  O0
+  DLY_MOD IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 3.0ns     TplhTY= 4.2ns    TplhMX= 5.6ns
+  TphlMN= 3.0ns     TphlTY= 4.0ns    TphlMX= 5.3ns
+  )
.ENDS  74F32


.SUBCKT 74HC32  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 or(2) DPWR DGND
+     1A 1B 1Y
+     DLY_HC32 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC32 ugate (tplhTY=10ns tplhMX=20ns tphlTY=10ns tphlMX=20ns)
.ENDS  74HC32


.SUBCKT 74HC32A A1 B1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 OR(2) DPWR DGND
+ A1 B1 Y1
+ DLY_HC32A IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HC32A UGATE (TPLHMX=15NS TPHLMX=15NS)
.ENDS 74HC32A


.SUBCKT 74HCT32  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 or(2) DPWR DGND
+     1A 1B 1Y
+     DLY_HCT32 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HCT32 ugate (tplhTY=15ns tplhMX=24ns tphlTY=15ns tphlMX=24ns)
.ENDS  74HCT32


.SUBCKT 74HCT32A A1 B1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 OR(2) DPWR DGND
+ A1 B1 Y1
+ DLY_HCT32A IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT32A UGATE (TPLHMX=20NS TPHLMX=20NS)
.ENDS 74HCT32A


.SUBCKT 74LS32  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 or(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS32 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS32 ugate (tplhTY=14ns tplhMX=22ns tphlTY=14ns tphlMX=22ns)
.ENDS  74LS32


.SUBCKT 74S32  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 or(2) DPWR DGND
+     1A 1B 1Y
+     DLY_S32 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S32 ugate (tplhTY=4ns tplhMX=7ns tphlTY=4ns tphlMX=7ns)
.ENDS  74S32


.SUBCKT 7433  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_33 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_33 ugate (tplhTY=10ns tplhMX=15ns tphlTY=12ns tphlMX=18ns)
.ENDS  7433


.SUBCKT 74ALS33A  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ALS33 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS33 ugate (tplhMN=10ns tplhMX=33ns tphlMN=2ns tphlMX=12ns)
.ENDS  74ALS33A


.SUBCKT 74LS33  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS33 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS33 ugate (tplhTY=20ns tplhMX=32ns tphlTY=18ns tphlMX=28ns)
.ENDS  74LS33


.SUBCKT 74AC34
+ 1A 1Y
+ OPTIONAL:  DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS:  MNTYMXDLY=0 IO_LEVEL=0
U1 BUF DPWR DGND
+ 1A 1Y
+ DLY IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY UGATE(TPLHMN=1.5NS TPLHTY=4NS TPLHMX=6.3NS
+                TPHLMN=1.5NS TPHLTY=4NS TPHLMX=6.2NS)
.ENDS 74AC34


.SUBCKT 74ACT34
+ 1A 1Y
+ OPTIONAL:  DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS:  MNTYMXDLY=0 IO_LEVEL=0
U1 BUF DPWR DGND
+ 1A 1Y
+ DLY IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY UGATE(TPLHMN=1.5NS TPLHTY=6.1NS TPLHMX=8.9NS
+                TPHLMN=1.5NS TPHLTY=5.2NS TPHLMX=8NS)
.ENDS 74ACT34


.SUBCKT 74ALS34  1A 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 buf  DPWR DGND
+     1A 1Y
+     DLY_ALS34 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS34 ugate (tplhMN=4ns tplhMX=15ns tphlMN=1ns tphlMX=10ns)
.ENDS  74ALS34


.SUBCKT 74AS34  1A 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 buf  DPWR DGND
+     1A 1Y
+     DLY_AS34 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS34 ugate (tplhMN=1ns tplhMX=5.5ns tphlMN=1ns tphlMX=6ns)
.ENDS  74AS34


.SUBCKT 74ALS35A  1A 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 buf  DPWR DGND
+     1A 1Y
+     DLY_ALS35 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS35 ugate (tplhMN=20ns tplhMX=50ns tphlMN=2ns tphlMX=14ns)
.ENDS  74ALS35A


.SUBCKT 74HC36  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_HC36 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC36 ugate (tplhTY=10ns tplhMX=20ns tphlTY=10ns tphlMX=20ns)
.ENDS  74HC36


.SUBCKT 7437  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_37 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_37 ugate (tplhTY=13ns tplhMX=22ns tphlTY=8ns tphlMX=15ns)
.ENDS  7437


.SUBCKT 74ALS37 1A 1B 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ 1A 1B 1Y
+ DLY_ALS37 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS37 UGATE (TPLHMN=2NS TPLHMX=9NS TPHLMX=3NS TPHLMX=11NS)
.ENDS 74ALS37


.SUBCKT 74ALS37A  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ALS37 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS37 ugate (tplhMN=2ns tplhMX=8ns tphlMN=2ns tphlMX=7ns)
.ENDS  74ALS37A


.SUBCKT 74F37 A0 B0 O0BAR
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ A0 B0
+ O0BAR
+ DLY_F37 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_F37 UGATE (TPLHMN=2NS TPLHTY=3.2ns TPLHMX=5.5NS
+                     TPHLMN=1.5NS TPHLTY=2.4 TPHLMX=4.5NS)
.ENDS 74F37


.SUBCKT 74LS37  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS37 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS37 ugate (tplhTY=12ns tplhMX=24ns tphlTY=12ns tphlMX=24ns)
.ENDS  74LS37


.SUBCKT 74S37  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_S37 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S37 ugate (tplhTY=4ns tplhMX=6.5ns tphlTY=4ns tphlMX=6.5ns)
.ENDS  74S37


.SUBCKT 7438  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_38 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_38 ugate (tplhTY=14ns tplhMX=22ns tphlTY=11ns tphlMX=18ns)
.ENDS  7438


.SUBCKT 74ALS38 1A 1B 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ 1A 1B 1Y
+ DLY_ALS38 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS38 UGATE (TPLHMN=6NS TPLHMX=23NS TPHLMX=6NS TPHLMX=18NS)
.ENDS 74ALS38


.SUBCKT 74ALS38A  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_ALS38 IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS38 ugate (tplhMN=10ns tplhMX=33ns tphlMN=2ns tphlMX=12ns)
.ENDS  74ALS38A


.SUBCKT  74F38   A0  B0  O0BAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u1 nand(2) DPWR DGND
+  A0  B0  O0BAR
+  DLY_MOD IO_F_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 6.5ns     TplhTY= 9.7ns    TplhMX= 12.5ns
+  TphlMN= 1.0ns     TphlTY= 2.1ns    TphlMX= 5.0ns
+  )
.ENDS  74F38


.SUBCKT 74LS38  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS38 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS38 ugate (tplhTY=20ns tplhMX=32ns tphlTY=18ns tphlMX=28ns)
.ENDS  74LS38


.SUBCKT 74S38  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_S38 IO_S_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S38 ugate (tplhTY=6.5ns tplhMX=10ns tphlTY=6.5ns tphlMX=10ns)
.ENDS  74S38


.SUBCKT 7439  1A 1B 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_39 IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_39 ugate (tplhMX=22ns tphlMX=18ns)
.ENDS  7439


.SUBCKT 7440  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_40 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_40 ugate (tplhTY=13ns tplhMX=22ns tphlTY=8ns tphlMX=15ns)
.ENDS  7440


.SUBCKT 74ALS40A  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_ALS40 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS40 ugate (tplhMN=2ns tplhMX=8ns tphlMN=2ns tphlMX=7ns)
.ENDS  74ALS40A


.SUBCKT 74F40 A0 B0 C0 D0 O0BAR
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(4) DPWR DGND
+ A0 B0 C0 D0
+ O0BAR
+ DLY_F40 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_F40 UGATE (TPLHMN=2NS TPLHTY=3ns TPLHMX=6NS
+                     TPHLMN=1.5NS TPHLTY=2.5ns TPHLMX=5NS)
.ENDS 74F40


.SUBCKT 74H40  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_H40 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H40 ugate (tplhTY=8.5ns tplhMX=12ns tphlTY=6.5ns tphlMX=12ns)
.ENDS  74H40


.SUBCKT 74LS40  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_LS40 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS40 ugate (tplhTY=12ns tplhMX=24ns tphlTY=12ns tphlMX=24ns)
.ENDS  74LS40


.SUBCKT 74S40  1A 1B 1C 1D 1Y
+     optional: DPWR=$G_DPWR DGND=$G_DGND
+     params: MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_S40 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S40 ugate (tplhTY=4ns tplhMX=6.5ns tphlTY=4ns tphlMX=6.5ns)
.ENDS  74S40


.SUBCKT 7442A  A B C D
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+      optional: DPWR=$G_DPWR DGND=$G_DGND
+      params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP (4,10) DPWR DGND
+      A B C D
+      O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+      D0_GATE IO_STD IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     dbar = {~D}
+
+     O0_O = {~(abar & bbar & cbar & dbar)}
+     O1_O = {~(A & bbar & cbar & dbar)}
+     O2_O = {~(abar & B & cbar & dbar)}
+     O3_O = {~(A & B & cbar & dbar)}
+     O4_O = {~(abar & bbar & C & dbar)}
+     O5_O = {~(A & bbar & C & dbar)}
+     O6_O = {~(abar & B & C & dbar)}
+     O7_O = {~(A & B & C & dbar)}
+     O8_O = {~(abar & bbar & cbar & D)}
+     O9_O = {~(A & bbar & cbar & D)}
U2 PINDLY (10,0,4) DPWR DGND
+      O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+      A B C D
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+      IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+      ATRAN = {CHANGED(A,0)}
+      BTRAN = {CHANGED(B,0)}
+      CTRAN = {CHANGED(C,0)}
+      DTRAN = {CHANGED(D,0)}
+
+  PINDLY:
+      O0 = {
+        CASE(
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,14ns,25ns))}
+
+      O1 = {
+        CASE(
+           ATRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O2 = {
+        CASE(
+           BTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O3 = {
+        CASE(
+           ATRAN | BTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O4 = {
+        CASE(
+           CTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O5 = {
+        CASE(
+           ATRAN | CTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O6 = {
+        CASE(
+           BTRAN | CTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O7 = {
+        CASE(
+           ATRAN | BTRAN | CTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O8 = {
+        CASE(
+           DTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O9 = {
+        CASE(
+           ATRAN | DTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
.ENDS 7442A


.SUBCKT 74HC42  A B C D
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+      optional: DPWR=$G_DPWR DGND=$G_DGND
+      params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP (4,10) DPWR DGND
+      A B C D
+      O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+      D0_GATE IO_HC IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     dbar = {~D}
+
+     O0_O = {~(abar & bbar & cbar & dbar)}
+     O1_O = {~(A & bbar & cbar & dbar)}
+     O2_O = {~(abar & B & cbar & dbar)}
+     O3_O = {~(A & B & cbar & dbar)}
+     O4_O = {~(abar & bbar & C & dbar)}
+     O5_O = {~(A & bbar & C & dbar)}
+     O6_O = {~(abar & B & C & dbar)}
+     O7_O = {~(A & B & C & dbar)}
+     O8_O = {~(abar & bbar & cbar & D)}
+     O9_O = {~(A & bbar & cbar & D)}
U2 PINDLY (10,0,0) DPWR DGND
+      O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+      IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 = {
+            DELAY(-1,18ns,30ns)}
.ENDS 74HC42


.SUBCKT 74HCT42  A0 A1 A2 A3
+      Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
+      optional: DPWR=$G_DPWR DGND=$G_DGND
+      params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP (4,10) DPWR DGND
+      A0 A1 A2 A3
+      Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O
+      D0_GATE IO_HCT IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A0}
+     bbar = {~A1}
+     cbar = {~A2}
+     dbar = {~A3}
+
+     Y0_O = {~(abar & bbar & cbar & dbar)}
+     Y1_O = {~(A0 & bbar & cbar & dbar)}
+     Y2_O = {~(abar & A1 & cbar & dbar)}
+     Y3_O = {~(A0 & A1 & cbar & dbar)}
+     Y4_O = {~(abar & bbar & A2 & dbar)}
+     Y5_O = {~(A0 & bbar & A2 & dbar)}
+     Y6_O = {~(abar & A1 & A2 & dbar)}
+     Y7_O = {~(A0 & A1 & A2 & dbar)}
+     Y8_O = {~(abar & bbar & cbar & A3)}
+     Y9_O = {~(A0 & bbar & cbar & A3)}
U2 PINDLY (10,0,0) DPWR DGND
+      Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O Y8_O Y9_O
+      Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
+      IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+      Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 = {
+            DELAY(-1,20ns,35ns)}
.ENDS 74HCT42


.SUBCKT 74LS42  A B C D
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+      optional: DPWR=$G_DPWR DGND=$G_DGND
+      params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP (4,10) DPWR DGND
+      A B C D
+      O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+      D0_GATE IO_LS IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     dbar = {~D}
+
+     O0_O = {~(abar & bbar & cbar & dbar)}
+     O1_O = {~(A & bbar & cbar & dbar)}
+     O2_O = {~(abar & B & cbar & dbar)}
+     O3_O = {~(A & B & cbar & dbar)}
+     O4_O = {~(abar & bbar & C & dbar)}
+     O5_O = {~(A & bbar & C & dbar)}
+     O6_O = {~(abar & B & C & dbar)}
+     O7_O = {~(A & B & C & dbar)}
+     O8_O = {~(abar & bbar & cbar & D)}
+     O9_O = {~(A & bbar & cbar & D)}
U2 PINDLY (10,0,4) DPWR DGND
+      O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+      A B C D
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+      IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+      ATRAN = {CHANGED(A,0)}
+      BTRAN = {CHANGED(B,0)}
+      CTRAN = {CHANGED(C,0)}
+      DTRAN = {CHANGED(D,0)}
+
+  PINDLY:
+      O0 = {
+        CASE(
+           TRN_LH, DELAY(-1,15ns,25ns),
+           TRN_HL, DELAY(-1,15ns,25ns),
+          DELAY(-1,15ns,25ns))}
+
+      O1 = {
+        CASE(
+           ATRAN, DELAY(-1,20ns,30ns),
+           TRN_LH, DELAY(-1,15ns,25ns),
+           TRN_HL, DELAY(-1,15ns,25ns),
+          DELAY(-1,20ns,30ns))}
+
+      O2 = {
+        CASE(
+           BTRAN, DELAY(-1,20ns,30ns),
+           TRN_LH, DELAY(-1,15ns,25ns),
+           TRN_HL, DELAY(-1,15ns,25ns),
+          DELAY(-1,20ns,30ns))}
+
+      O3 = {
+        CASE(
+           ATRAN | BTRAN, DELAY(-1,20ns,30ns),
+           TRN_LH, DELAY(-1,15ns,25ns),
+           TRN_HL, DELAY(-1,15ns,25ns),
+          DELAY(-1,20ns,30ns))}
+
+      O4 = {
+        CASE(
+           CTRAN, DELAY(-1,20ns,30ns),
+           TRN_LH, DELAY(-1,15ns,25ns),
+           TRN_HL, DELAY(-1,15ns,25ns),
+          DELAY(-1,20ns,30ns))}
+
+      O5 = {
+        CASE(
+           ATRAN | CTRAN, DELAY(-1,20ns,30ns),
+           TRN_LH, DELAY(-1,15ns,25ns),
+           TRN_HL, DELAY(-1,15ns,25ns),
+          DELAY(-1,20ns,30ns))}
+
+      O6 = {
+        CASE(
+           BTRAN | CTRAN, DELAY(-1,20ns,30ns),
+           TRN_LH, DELAY(-1,15ns,25ns),
+           TRN_HL, DELAY(-1,15ns,25ns),
+          DELAY(-1,20ns,30ns))}
+
+      O7 = {
+        CASE(
+           ATRAN | BTRAN | CTRAN, DELAY(-1,20ns,30ns),
+           TRN_LH, DELAY(-1,15ns,25ns),
+           TRN_HL, DELAY(-1,15ns,25ns),
+          DELAY(-1,20ns,30ns))}
+
+      O8 = {
+        CASE(
+           DTRAN, DELAY(-1,20ns,30ns),
+           TRN_LH, DELAY(-1,15ns,25ns),
+           TRN_HL, DELAY(-1,15ns,25ns),
+          DELAY(-1,20ns,30ns))}
+
+      O9 = {
+        CASE(
+           ATRAN | DTRAN, DELAY(-1,20ns,30ns),
+           TRN_LH, DELAY(-1,15ns,25ns),
+           TRN_HL, DELAY(-1,15ns,25ns),
+          DELAY(-1,20ns,30ns))}
.ENDS 74LS42


.SUBCKT 7443A  A B C D
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+      optional: DPWR=$G_DPWR DGND=$G_DGND
+      params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP (4,10) DPWR DGND
+      A B C D
+      O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+      D0_GATE IO_STD IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     dbar = {~D}
+
+     O0_O = {~(A & B & cbar & dbar)}
+     O1_O = {~(abar & bbar & C & dbar)}
+     O2_O = {~(A & bbar & C & dbar)}
+     O3_O = {~(abar & B & C & dbar)}
+     O4_O = {~(A & B & C & dbar)}
+     O5_O = {~(abar & bbar & cbar & D)}
+     O6_O = {~(A & bbar & cbar & D)}
+     O7_O = {~(abar & B & cbar & D)}
+     O8_O = {~(A & B & cbar & D)}
+     O9_O = {~(abar & bbar & C & D)}
U2 PINDLY (10,0,4) DPWR DGND
+      O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+      A B C D
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+      IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+      ATRAN = {CHANGED(A,0)}
+      BTRAN = {CHANGED(B,0)}
+      CTRAN = {CHANGED(C,0)}
+      DTRAN = {CHANGED(D,0)}
+
+  PINDLY:
+      O0 = {
+        CASE(
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,14ns,25ns))}
+
+      O1 = {
+        CASE(
+           ATRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O2 = {
+        CASE(
+           BTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O3 = {
+        CASE(
+           ATRAN | BTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O4 = {
+        CASE(
+           CTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O5 = {
+        CASE(
+           ATRAN | CTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O6 = {
+        CASE(
+           BTRAN | CTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O7 = {
+        CASE(
+           ATRAN | BTRAN | CTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O8 = {
+        CASE(
+           DTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O9 = {
+        CASE(
+           ATRAN | DTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
.ENDS 7443A


.SUBCKT 7444A  A B C D
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+      optional: DPWR=$G_DPWR DGND=$G_DGND
+      params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP (4,10) DPWR DGND
+      A B C D
+      O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+      D0_GATE IO_STD IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     dbar = {~D}
+
+     O0_O = {~(abar & B & cbar & dbar)}
+     O1_O = {~(abar & B & C & dbar)}
+     O2_O = {~(A & B & C & dbar)}
+     O3_O = {~(A & bbar & C & dbar)}
+     O4_O = {~(abar & bbar & C & dbar)}
+     O5_O = {~(abar & bbar & C & D)}
+     O6_O = {~(A & bbar & C & D)}
+     O7_O = {~(A & B & C & D)}
+     O8_O = {~(abar & B & C & D)}
+     O9_O = {~(abar & B & cbar & D)}
U2 PINDLY (10,0,4) DPWR DGND
+      O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+      A B C D
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+      IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+      ATRAN = {CHANGED(A,0)}
+      BTRAN = {CHANGED(B,0)}
+      CTRAN = {CHANGED(C,0)}
+      DTRAN = {CHANGED(D,0)}
+
+  PINDLY:
+      O0 = {
+        CASE(
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,14ns,25ns))}
+
+      O1 = {
+        CASE(
+           ATRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O2 = {
+        CASE(
+           BTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O3 = {
+        CASE(
+           ATRAN | BTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O4 = {
+        CASE(
+           CTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O5 = {
+        CASE(
+           ATRAN | CTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O6 = {
+        CASE(
+           BTRAN | CTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O7 = {
+        CASE(
+           ATRAN | BTRAN | CTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O8 = {
+        CASE(
+           DTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
+
+      O9 = {
+        CASE(
+           ATRAN | DTRAN, DELAY(-1,17ns,30ns),
+           TRN_LH, DELAY(-1,10ns,25ns),
+           TRN_HL, DELAY(-1,14ns,25ns),
+          DELAY(-1,17ns,30ns))}
.ENDS 7444A


.SUBCKT 7445  A B C D
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+      optional: DPWR=$G_DPWR DGND=$G_DGND
+      params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP (4,10) DPWR DGND
+      A B C D
+      O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+      D0_GATE IO_STD IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     dbar = {~D}
+
+     O0_O = {~(abar & bbar & cbar & dbar)}
+     O1_O = {~(A & bbar & cbar & dbar)}
+     O2_O = {~(abar & B & cbar & dbar)}
+     O3_O = {~(A & B & cbar & dbar)}
+     O4_O = {~(abar & bbar & C & dbar)}
+     O5_O = {~(A & bbar & C & dbar)}
+     O6_O = {~(abar & B & C & dbar)}
+     O7_O = {~(A & B & C & dbar)}
+     O8_O = {~(abar & bbar & cbar & D)}
+     O9_O = {~(A & bbar & cbar & D)}
U2 PINDLY (10,0,4) DPWR DGND
+      O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+      A B C D
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+      IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+      O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 = {
+           DELAY(-1,-1,50ns)}
.ENDS 7445


.SUBCKT 7446A  A B C D BI/RBO RBIBAR LTBAR
+      OA OB OC OD OE OF OG
+      optional: DPWR=$G_DPWR DGND=$G_DGND
+      params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP (7,8) DPWR DGND
+      A B C D BI/RBO RBIBAR LTBAR
+      O_A O_B O_C O_D O_E O_F O_G BI/RBO
+      D0_GATE IO_STD IO_LEVEL={IO_LEVEL}
+
+    LOGIC:
+      alt = {~(A & LTBAR)}
+      blt = {~(B & LTBAR)}
+      clt = {~(C & LTBAR)}
+      dbar = {~D}
+      abi = {~(alt & BI/RBO)}
+      bbi = {~(blt & BI/RBO)}
+      cbi = {~(clt & BI/RBO)}
+      dbi = {~(dbar & BI/RBO)}
+      rbi = {~RBIBAR}
+
+      O_A = {(bbi & dbi) | (alt & cbi) | (abi & blt & clt & dbar)}
+      O_B = {(bbi & dbi) | (abi & blt & cbi) | (alt & bbi & cbi)}
+      O_C = {(cbi & dbi) | (alt & bbi & clt)}
+      O_D = {(abi & blt & clt) | (alt & blt & cbi) | (abi & bbi & cbi)}
+      O_E = {abi | (blt & cbi)}
+      O_F  = {(abi & bbi) | (bbi & clt) | (abi & clt & dbar)}
+      O_G = {(abi & bbi & cbi) | (blt & clt & dbar & LTBAR)}
+      BI/RBO = {~(LTBAR & rbi & dbar & clt & blt & alt)}
U2 PINDLY (7,0,0) DPWR DGND
+    O_A O_B O_C O_D O_E O_F O_G
+    OA OB OC OD OE OF OG
+    IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     OA OB OC OD OE OF OG = {
+         DELAY(-1,-1,100ns)}
.ENDS 7446A


.SUBCKT 7447A  A B C D BI/RBO RBIBAR LTBAR
+      OA OB OC OD OE OF OG
+      optional: DPWR=$G_DPWR DGND=$G_DGND
+      params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP (7,8) DPWR DGND
+      A B C D BI/RBO RBIBAR LTBAR
+      O_A O_B O_C O_D O_E O_F O_G BI/RBO
+      D0_GATE IO_STD IO_LEVEL={IO_LEVEL}
+
+    LOGIC:
+      alt = {~(A & LTBAR)}
+      blt = {~(B & LTBAR)}
+      clt = {~(C & LTBAR)}
+      dbar = {~D}
+      abi = {~(alt & BI/RBO)}
+      bbi = {~(blt & BI/RBO)}
+      cbi = {~(clt & BI/RBO)}
+      dbi = {~(dbar & BI/RBO)}
+      rbi = {~RBIBAR}
+
+      O_A = {(bbi & dbi) | (alt & cbi) | (abi & blt & clt & dbar)}
+      O_B = {(bbi & dbi) | (abi & blt & cbi) | (alt & bbi & cbi)}
+      O_C = {(cbi & dbi) | (alt & bbi & clt)}
+      O_D = {(abi & blt & clt) | (alt & blt & cbi) | (abi & bbi & cbi)}
+      O_E = {abi | (blt & cbi)}
+      O_F  = {(abi & bbi) | (bbi & clt) | (abi & clt & dbar)}
+      O_G = {(abi & bbi & cbi) | (blt & clt & dbar & LTBAR)}
+      BI/RBO = {~(LTBAR & rbi & dbar & clt & blt & alt)}
U2 PINDLY (7,0,0) DPWR DGND
+    O_A O_B O_C O_D O_E O_F O_G
+    OA OB OC OD OE OF OG
+    IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     OA OB OC OD OE OF OG = {
+         DELAY(-1,-1,100ns)}
.ENDS 7447A


.SUBCKT 74LS47  A B C D BI/RBO RBIBAR LTBAR
+      OA OB OC OD OE OF OG
+      optional: DPWR=$G_DPWR DGND=$G_DGND
+      params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP (7,8) DPWR DGND
+      A B C D BI/RBO RBIBAR LTBAR
+      O_A O_B O_C O_D O_E O_F O_G BI/RBO
+      D0_GATE IO_LS IO_LEVEL={IO_LEVEL}
+
+    LOGIC:
+      alt = {~(A & LTBAR)}
+      blt = {~(B & LTBAR)}
+      clt = {~(C & LTBAR)}
+      dbar = {~D}
+      abi = {~(alt & BI/RBO)}
+      bbi = {~(blt & BI/RBO)}
+      cbi = {~(clt & BI/RBO)}
+      dbi = {~(dbar & BI/RBO)}
+      rbi = {~RBIBAR}
+
+      O_A = {(bbi & dbi) | (alt & cbi) | (abi & blt & clt & dbar)}
+      O_B = {(bbi & dbi) | (abi & blt & cbi) | (alt & bbi & cbi)}
+      O_C = {(cbi & dbi) | (alt & bbi & clt)}
+      O_D = {(abi & blt & clt) | (alt & blt & cbi) | (abi & bbi & cbi)}
+      O_E = {abi | (blt & cbi)}
+      O_F  = {(abi & bbi) | (bbi & clt) | (abi & clt & dbar)}
+      O_G = {(abi & bbi & cbi) | (blt & clt & dbar & LTBAR)}
+      BI/RBO = {~(LTBAR & rbi & dbar & clt & blt & alt)}
U2 PINDLY (7,0,0) DPWR DGND
+    O_A O_B O_C O_D O_E O_F O_G
+    OA OB OC OD OE OF OG
+    IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     OA OB OC OD OE OF OG = {
+         DELAY(-1,-1,100ns)}
.ENDS 74LS47


.SUBCKT 7448  A B C D BI/RBO RBIBAR LTBAR
+      OA OB OC OD OE OF OG
+      optional: DPWR=$G_DPWR DGND=$G_DGND
+      params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP (7,8) DPWR DGND
+      A B C D BI/RBO RBIBAR LTBAR
+      O_A O_B O_C O_D O_E O_F O_G BI/RBO
+      D0_GATE IO_STD IO_LEVEL={IO_LEVEL}
+
+    LOGIC:
+      alt = {~(A & LTBAR)}
+      blt = {~(B & LTBAR)}
+      clt = {~(C & LTBAR)}
+      dbar = {~D}
+      abi = {~(alt & BI/RBO)}
+      bbi = {~(blt & BI/RBO)}
+      cbi = {~(clt & BI/RBO)}
+      dbi = {~(dbar & BI/RBO)}
+      rbi = {~RBIBAR}
+
+      O_A = {~((bbi & dbi) | (alt & cbi) | (abi & blt & clt & dbar))}
+      O_B = {~((bbi & dbi) | (abi & blt & cbi) | (alt & bbi & cbi))}
+      O_C = {~((cbi & dbi) | (alt & bbi & clt))}
+      O_D = {~((abi & blt & clt) | (alt & blt & cbi) | (abi & bbi & cbi))}
+      O_E = {~(abi | (blt & cbi))}
+      O_F  = {~((abi & bbi) | (bbi & clt) | (abi & clt & dbar))}
+      O_G = {~((abi & bbi & cbi) | (blt & clt & dbar & LTBAR))}
+      BI/RBO = {~(LTBAR & rbi & dbar & clt & blt & alt)}
U2 PINDLY (7,0,0) DPWR DGND
+    O_A O_B O_C O_D O_E O_F O_G
+    OA OB OC OD OE OF OG
+    IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     OA OB OC OD OE OF OG = {
+         DELAY(-1,-1,100ns)}
.ENDS 7448


.SUBCKT 74LS48  A B C D BI/RBO RBIBAR LTBAR
+      OA OB OC OD OE OF OG
+      optional: DPWR=$G_DPWR DGND=$G_DGND
+      params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP (7,8) DPWR DGND
+      A B C D BI/RBO RBIBAR LTBAR
+      O_A O_B O_C O_D O_E O_F O_G BI/RBO
+      D0_GATE IO_LS IO_LEVEL={IO_LEVEL}
+
+    LOGIC:
+      alt = {~(A & LTBAR)}
+      blt = {~(B & LTBAR)}
+      clt = {~(C & LTBAR)}
+      dbar = {~D}
+      abi = {~(alt & BI/RBO)}
+      bbi = {~(blt & BI/RBO)}
+      cbi = {~(clt & BI/RBO)}
+      dbi = {~(dbar & BI/RBO)}
+      rbi = {~RBIBAR}
+
+      O_A = {~((bbi & dbi) | (alt & cbi) | (abi & blt & clt & dbar))}
+      O_B = {~((bbi & dbi) | (abi & blt & cbi) | (alt & bbi & cbi))}
+      O_C = {~((cbi & dbi) | (alt & bbi & clt))}
+      O_D = {~((abi & blt & clt) | (alt & blt & cbi) | (abi & bbi & cbi))}
+      O_E = {~(abi | (blt & cbi))}
+      O_F  = {~((abi & bbi) | (bbi & clt) | (abi & clt & dbar))}
+      O_G = {~((abi & bbi & cbi) | (blt & clt & dbar & LTBAR))}
+      BI/RBO = {~(LTBAR & rbi & dbar & clt & blt & alt)}
U2 PINDLY (7,0,0) DPWR DGND
+    O_A O_B O_C O_D O_E O_F O_G
+    OA OB OC OD OE OF OG
+    IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     OA OB OC OD OE OF OG = {
+         DELAY(-1,-1,100ns)}
.ENDS 74LS48


.SUBCKT 74LS49  A B C D BIBAR
+      OA OB OC OD OE OF OG
+      optional: DPWR=$G_DPWR DGND=$G_DGND
+      params: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP (5,7) DPWR DGND
+      A B C D BIBAR
+      O_A O_B O_C O_D O_E O_F O_G 
+      D0_GATE IO_LS IO_LEVEL={IO_LEVEL}
+
+    LOGIC:
+      abar = {~A}
+      bbar = {~B}
+      cbar = {~C}
+      dbar = {~D}
+      abi = {~(abar & BIBAR)}
+      bbi = {~(bbar & BIBAR)}
+      cbi = {~(cbar & BIBAR)}
+      dbi = {~(dbar & BIBAR)}
+
+      O_A = {~((bbi & dbi) | (abar & cbi) | (abi & bbar & cbar & dbar))}
+      O_B = {~((bbi & dbi) | (abi & bbar & cbi) | (abar & bbi & cbi))}
+      O_C = {~((cbi & dbi) | (abar & bbi & cbar))}
+      O_D = {~((abi & bbar & cbar) | (abar & bbar & cbi) | (abi & bbi & cbi))}
+      O_E = {~(abi | (bbar & cbi))}
+      O_F  = {~((abi & bbi) | (bbi & cbar) | (abi & cbar & dbar))}
+      O_G = {~((abi & bbi & cbi) | (bbar & cbar & dbar))}
U2 PINDLY (7,0,0) DPWR DGND
+    O_A O_B O_C O_D O_E O_F O_G
+    OA OB OC OD OE OF OG
+    IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     OA OB OC OD OE OF OG = {
+         DELAY(-1,-1,100ns)}
.ENDS 74LS49


.SUBCKT 7450 1A 1B 1C 1D 1X 1XBAR 2A 2B 2C 2D 1Y 2Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+    1XBAR 1XB
+    D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 aoi(2,3) DPWR DGND
+    1A 1B
+    1C 1D
+    1X 1XB
+    1Y
+    DLY_50 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 aoi(2,2) DPWR DGND
+    2A 2B
+    2C 2D
+    2Y
+    DLY_50 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_50 ugate (tplhTY=13ns tplhMX=22ns tphlTY=8ns tphlMX=15ns)
.ENDS 7450


.SUBCKT 74H50 1A 1B 1C 1D 1X 1XBAR 2A 2B 2C 2D 1Y 2Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+    1XBAR 1XB
+    D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 aoi(2,3) DPWR DGND
+    1A 1B
+    1C 1D
+    1X 1XB
+    1Y
+    DLY_H50 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 aoi(2,2) DPWR DGND
+    2A 2B
+    2C 2D
+    2Y
+    DLY_H50 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H50 ugate (tplhTY=6.8ns tplhMX=11ns tphlTY=6.2ns tphlMX=11ns)
.ENDS 74H50


.SUBCKT 7451 1A 1B 1C 1D 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 aoi(2,2) DPWR DGND
+    1A 1B
+    1C 1D
+    1Y
+    DLY_51 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_51 ugate (tplhTY=13ns tplhMX=22ns tphlTY=8ns tphlMX=15ns)
.ENDS 7451


.SUBCKT 74F51 1A 1B 1C 1D 1E 1F 2A 2B 2C 2D 1Y 2Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 aoi(3,2) DPWR DGND
+    1A 1B 1C
+    1D 1E 1F
+    1Y
+    DLY_F51 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 aoi(2,2) DPWR DGND
+    2A 2B
+    2C 2D
+    2Y
+    DLY_F51 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_F51 ugate (tplhMN=2ns tplhTY=3.5ns tplhMX=5.5ns
+		           tphlMN=1ns tphlTY=2.5ns tphlMX=4ns)
.ENDS 74F51


.SUBCKT 74H51 1A 1B 1C 1D 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 aoi(2,2) DPWR DGND
+    1A 1B
+    1C 1D
+    1Y
+    DLY_H51 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H51 ugate (tplhTY=6.8ns tplhMX=11ns tphlTY=6.2ns tphlMX=11ns)
.ENDS 74H51


.SUBCKT 74HC51 1A 1B 1C 1D 1E 1F 2A 2B 2C 2D 1Y 2Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 aoi(3,2) DPWR DGND
+    1A 1B 1C
+    1D 1E 1F
+    1Y
+    DLY_HC51 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 aoi(2,2) DPWR DGND
+    2A 2B
+    2C 2D
+    2Y
+    DLY_HC51 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC51 ugate (tplhTY=15ns tplhMX=28ns tphlTY=15ns tphlMX=28ns)
.ENDS 74HC51


.SUBCKT 74LS51 1A 1B 1C 1D 1E 1F 2A 2B 2C 2D 1Y 2Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 aoi(3,2) DPWR DGND
+    1A 1B 1C
+    1D 1E 1F
+    1Y
+    DLY_LS51 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 aoi(2,2) DPWR DGND
+    2A 2B
+    2C 2D
+    2Y
+    DLY_LS51 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS51 ugate (tplhTY=12ns tplhMX=20ns tphlTY=12.5ns tphlMX=20ns)
.ENDS 74LS51


.SUBCKT 74S51 1A 1B 1C 1D 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 aoi(2,2) DPWR DGND
+    1A 1B
+    1C 1D
+    1Y
+    DLY_S51 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S51 ugate (tplhTY=3.5ns tplhMX=5.5ns tphlTY=3.5ns tphlMX=5.5ns)
.ENDS 74S51


.SUBCKT 74H52 A B C D E F G H I X Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 ao(3,5) DPWR DGND
+    A B $D_HI
+    C D E
+    F G $D_HI
+    H I $D_HI
+    X $D_HI $D_HI
+    Y
+    DLY_H52 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H52 ugate (tplhTY=10.6ns tplhMX=15ns tphlTY=9.2ns tphlMX=15ns)
.ENDS 74H52


.SUBCKT 7453 A B C D E F G H X XBAR Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+    XBAR XB
+    D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 aoi(2,5) DPWR DGND
+    A B
+    C D
+    E F
+    G H
+    X XB
+    Y
+    DLY_53 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_53 ugate (tplhTY=13ns tplhMX=22ns tphlTY=8ns tphlMX=15ns)
.ENDS 7453


.SUBCKT 74H53 A B C D E F G H I X XBAR Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+    XBAR XB
+    D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 aoi(3,5) DPWR DGND
+    A B $D_HI
+    C D $D_HI
+    E F G
+    H I $D_HI
+    X XB $D_HI
+    Y
+    DLY_H53 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H53 ugate (tplhTY=7ns tplhMX=11ns tphlTY=6.2ns tphlMX=11ns)
.ENDS 74H53


.SUBCKT 7454 A B C D E F G H Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 aoi(2,4) DPWR DGND
+    A B
+    C D
+    E F
+    G H
+    Y
+    DLY_54 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_54 ugate (tplhTY=13ns tplhMX=22ns tphlTY=8ns tphlMX=15ns)
.ENDS 7454


.SUBCKT 74H54 A B C D E F G H I Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 aoi(3,4) DPWR DGND
+    A B $D_HI
+    C D $D_HI
+    E F G
+    H I $D_HI
+    Y
+    DLY_H54 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H54 ugate (tplhTY=7ns tplhMX=11ns tphlTY=6.2ns tphlMX=11ns)
.ENDS 74H54


.SUBCKT 74LS54 A B C D E F G H I J Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 aoi(3,4) DPWR DGND
+    A B $D_HI
+    C D E
+    F G H
+    I J $D_HI
+    Y
+    DLY_LS54 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS54 ugate (tplhTY=12ns tplhMX=20ns tphlTY=12.5ns tphlMX=20ns)
.ENDS 74LS54


.SUBCKT 74H55 A B C D E F G H X XBAR Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+    XBAR XB
+    D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 aoi(4,3) DPWR DGND
+    A B C D
+    E F G H
+    X XB $D_HI $D_HI
+    Y
+    DLY_H55 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_H55 ugate (tplhTY=7ns tplhMX=11ns tphlTY=6.5ns tphlMX=11ns)
.ENDS 74H55


.SUBCKT 74LS55 A B C D E F G H Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 aoi(4,2) DPWR DGND
+    A B C D
+    E F G H
+    Y
+    DLY_LS55 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS55 ugate (tplhTY=12ns tplhMX=20ns tphlTY=12.5ns tphlMX=20ns)
.ENDS 74LS55


.SUBCKT 74LS56 CLR CLKA CLKB QA QB QC
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     $D_HI CLRBAR CLK1 $D_HI $D_HI Q1 Q1BAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     $D_HI CLRBAR Q1 $D_HI $D_HI $D_NC Q2BAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     $D_HI CLRBAR CLK2 $D_HI $D_HI QA_O QABAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     $D_HI CLRBAR CLK3 $D_HI $D_HI Q3 Q3BAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5 JKFF(1) DPWR DGND
+     $D_HI CLRBAR Q3 $D_HI $D_HI $D_NC Q4BAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6 JKFF(1) DPWR DGND
+     $D_HI CLRBAR CLK4 $D_HI $D_HI QB_O QBBAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U7 JKFF(1) DPWR DGND
+     $D_HI CLRBAR QB_O $D_HI $D_HI QC_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U8LOG LOGICEXP(11,5) DPWR DGND
+     CLR CLKA Q1 Q1BAR Q2BAR QABAR CLKB Q3 Q3BAR Q4BAR QBBAR
+     CLK1 CLK2 CLK3 CLK4 CLRBAR
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     CLRBAR = {~CLR}
+     CLK1 = {CLKA & QABAR}
+     CLK2 = {CLKA & (~((Q1BAR & QABAR) | (Q2BAR & QABAR)))}
+     CLK3 = {CLKB & QBBAR}
+     CLK4 = {CLKB & (~((Q3BAR & QBBAR) | (Q4BAR & QBBAR)))}
U9DLY PINDLY(3,0,3) DPWR DGND
+     QA_O QB_O QC_O
+     CLR CLKA CLKB
+     QA QB QC
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     CLEAR = {CHANGED_LH(CLR,0)}
+     CLOCKA = {CHANGED_HL(CLKA,0)}
+     CLOCKB = {CHANGED_HL(CLKB,0)}
+
+  PINDLY:
+     QA = {
+        CASE(
+           CLEAR & TRN_HL, DELAY(-1,17ns,30ns),
+           CLOCKA & TRN_LH, DELAY(-1,12ns,20ns),
+           CLOCKA & TRN_HL, DELAY(-1,14ns,25ns),
+           DELAY(-1,18ns,31ns))}
+
+     QB = {
+        CASE(
+           CLEAR & TRN_HL, DELAY(-1,17ns,30ns),
+           CLOCKB & TRN_LH, DELAY(-1,8ns,15ns),
+           CLOCKB & TRN_HL, DELAY(-1,14ns,25ns),
+           DELAY(-1,18ns,31ns))}
+
+     QC = {
+        CASE(
+           CLEAR & TRN_HL, DELAY(-1,17ns,30ns),
+           CLOCKB & TRN_LH, DELAY(-1,18ns,30ns),
+           CLOCKB & TRN_HL, DELAY(-1,24ns,35ns),
+           DELAY(-1,25ns,36ns))}
U10CON CONSTRAINT(3) DPWR DGND
+     CLKA CLKB CLR
+     IO_LS IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CLKA
+     MAXFREQ=15MEG
+
+  FREQ:
+     NODE=CLKB
+     MAXFREQ=15MEG
+
+  WIDTH:
+     NODE=CLKA
+     MIN_HI=30ns
+     MIN_LO=30ns
+
+  WIDTH:
+     NODE=CLKB
+     MIN_HI=30ns
+     MIN_LO=30ns
+
+  WIDTH:
+     NODE=CLR
+     MIN_HI=30ns
+
+  SETUP_HOLD:
+     CLOCK HL=CLKA
+     DATA(1)=CLR
+     SETUPTIME_LO=25ns
+
+  SETUP_HOLD:
+     CLOCK HL=CLKB
+     DATA(1)=CLR
+     SETUPTIME_LO=25ns
.ENDS 74LS56


.SUBCKT 74LS57 CLR CLKA CLKB QA QB QC
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     $D_HI CLRBAR CLKA Q2BAR $D_HI Q1 $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     $D_HI CLRBAR CLKA Q1 $D_HI Q2 Q2BAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     $D_HI CLRBAR Q2 $D_HI $D_HI QA_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     $D_HI CLRBAR CLK3 $D_HI $D_HI Q3 Q3BAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5 JKFF(1) DPWR DGND
+     $D_HI CLRBAR Q3 $D_HI $D_HI $D_NC Q4BAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6 JKFF(1) DPWR DGND
+     $D_HI CLRBAR CLK4 $D_HI $D_HI QB_O QBBAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U7 JKFF(1) DPWR DGND
+     $D_HI CLRBAR QB_O $D_HI $D_HI QC_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U8LOG LOGICEXP(6,3) DPWR DGND
+     CLR CLKB Q3 Q3BAR Q4BAR QBBAR
+     CLK3 CLK4 CLRBAR
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     CLRBAR = {~CLR}
+     CLK3 = {CLKB & QBBAR}
+     CLK4 = {CLKB & (~((Q3BAR & QBBAR) | (Q4BAR & QBBAR)))}
U9DLY PINDLY(3,0,3) DPWR DGND
+     QA_O QB_O QC_O
+     CLR CLKA CLKB
+     QA QB QC
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     CLEAR = {CHANGED_LH(CLR,0)}
+     CLOCKA = {CHANGED_HL(CLKA,0)}
+     CLOCKB = {CHANGED_HL(CLKB,0)}
+
+  PINDLY:
+     QA = {
+        CASE(
+           CLEAR & TRN_HL, DELAY(-1,17ns,30ns),
+           CLOCKA & TRN_LH, DELAY(-1,14ns,25ns),
+           CLOCKA & TRN_HL, DELAY(-1,18ns,30ns),
+           DELAY(-1,19ns,31ns))}
+
+     QB = {
+        CASE(
+           CLEAR & TRN_HL, DELAY(-1,17ns,30ns),
+           CLOCKB & TRN_LH, DELAY(-1,8ns,15ns),
+           CLOCKB & TRN_HL, DELAY(-1,14ns,25ns),
+           DELAY(-1,18ns,31ns))}
+
+     QC = {
+        CASE(
+           CLEAR & TRN_HL, DELAY(-1,17ns,30ns),
+           CLOCKB & TRN_LH, DELAY(-1,18ns,30ns),
+           CLOCKB & TRN_HL, DELAY(-1,24ns,35ns),
+           DELAY(-1,25ns,36ns))}
U10CON CONSTRAINT(3) DPWR DGND
+     CLKA CLKB CLR
+     IO_LS IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CLKA
+     MAXFREQ=15MEG
+
+  FREQ:
+     NODE=CLKB
+     MAXFREQ=15MEG
+
+  WIDTH:
+     NODE=CLKA
+     MIN_HI=30ns
+     MIN_LO=30ns
+
+  WIDTH:
+     NODE=CLKB
+     MIN_HI=30ns
+     MIN_LO=30ns
+
+  WIDTH:
+     NODE=CLR
+     MIN_HI=30ns
+
+  SETUP_HOLD:
+     CLOCK HL=CLKA
+     DATA(1)=CLR
+     SETUPTIME_LO=25ns
+
+  SETUP_HOLD:
+     CLOCK HL=CLKB
+     DATA(1)=CLR
+     SETUPTIME_LO=25ns
.ENDS 74LS57


.SUBCKT 74HC58 A1 B1 C1 D1 E1 F1 Y1 A2 B2 C2 D2 Y2
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(10,2) DPWR DGND
+ A1 B1 C1 D1 E1 F1 A2 B2 C2 D2
+ Y1 Y2
+ DLY_HC58 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+   Y1 = {(A1 & B1 & C1) | (D1 & E1 & F1)}
+   Y2 = {(A2 & B2) | (C2 & D2)}
.MODEL DLY_HC58 UGATE(TPLHMX=25NS TPHLMX=25NS)
.ENDS 74HC58


.SUBCKT 7460 A B C D X XBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 and(4) DPWR DGND
+    A B C D
+    X
+    D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 inv DPWR DGND
+    X XBAR
+    D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.ENDS 7460


.SUBCKT 74H60 A B C D X XBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 and(4) DPWR DGND
+    A B C D
+    X
+    D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 inv DPWR DGND
+    X XBAR
+    D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.ENDS 74H60


.SUBCKT 74H61 A B C X 
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 and(3) DPWR DGND
+    A B C
+    X
+    D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.ENDS 74H61


.SUBCKT 74H62 A B C D E F G H I J X XBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 ao(3,4) DPWR DGND
+    A B $D_HI
+    C D E
+    F G H
+    I J $D_HI
+    X
+    D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 inv DPWR DGND
+    X XBAR
+    D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.ENDS 74H62


.SUBCKT  74F64   A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 D0 OBAR
+  optional: DPWR=$G_DPWR DGND=$G_DGND
+  params: MNTYMXDLY=0 IO_LEVEL=0
u0 aoi(4,4) DPWR DGND
+  A0   B0   C0     D0
+  A1   B1   C1     $D_HI
+  A2   B2   $D_HI  $D_HI
+  A3   B3   $D_HI  $D_HI
+  OBAR
+  DLY_MOD IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_MOD ugate (
+  TplhMN= 2.5ns     TplhTY= 4.6ns    TplhMX= 6.5ns
+  TphlMN= 1.5ns     TphlTY= 3.2ns    TphlMX= 4.5ns
+  )
.ENDS  74F64


.SUBCKT 74S64 A B C D E F G H I J K Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 aoi(4,4) DPWR DGND
+    A B C D
+    E F $D_HI $D_HI
+    G H I $D_HI
+    J K $D_HI $D_HI
+    Y
+    DLY_S64 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S64 ugate (tplhTY=3.5ns tplhMX=5.5ns tphlTY=3.5ns tphlMX=5.5ns)
.ENDS 74S64


.SUBCKT 74S65 A B C D E F G H I J K Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 aoi(4,4) DPWR DGND
+    A B C D
+    E F $D_HI $D_HI
+    G H I $D_HI
+    J K $D_HI $D_HI
+    Y
+    DLY_S65 IO_S_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S65 ugate (tplhMN=2ns tplhTY=5ns tplhMX=7.5ns tphlMN=2ns tphlTY=5.5ns
+                                 tphlMX=8.5ns)
.ENDS 74S65


.SUBCKT 74LS68 1CLKA 1CLRBAR 1CLKB 2CLRBAR 2CLK
+     1QA 1QB 1QC 1QD 2QA 2QB 2QC 2QD
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1J JKFF(1) DPWR DGND
+ $D_HI 1CLRBAR 1CLKA $D_HI $D_HI 1QAL $D_NC
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2J JKFF(1) DPWR DGND
+ $D_HI 1CLRBAR 1CKB $D_HI $D_HI 1QBL 1QBBAR
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3J JKFF(1) DPWR DGND
+ $D_HI 1CLRBAR 1QBL $D_HI $D_HI 1QCL 1QCBAR
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4J JKFF(1) DPWR DGND
+ $D_HI 1CLRBAR 1CKD $D_HI $D_HI 1QDL 1QDBAR
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5J JKFF(1) DPWR DGND
+ $D_HI 2CLRBAR 2CLK $D_HI $D_HI 2QAL $D_NC
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6J JKFF(1) DPWR DGND
+ $D_HI 2CLRBAR 2CLKB $D_HI $D_HI 2QBL 2QBBAR
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U7J JKFF(1) DPWR DGND
+ $D_HI 2CLRBAR 2QBL $D_HI $D_HI 2QCL 2QCBAR
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U8J JKFF(1) DPWR DGND
+ $D_HI 2CLRBAR 2CLKD $D_HI $D_HI 2QDL 2QDBAR
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U1LOG LOGICEXP(8,4) DPWR DGND
+  1CLKB 1QBBAR 1QCBAR 1QDBAR 2QAL 2QBBAR 2QCBAR 2QDBAR
+  1CKB 1CKD 2CLKB 2CLKD
+  D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+    1CKB={1CLKB&1QDBAR}
+    1CKD={1CLKB&(~((1QDBAR&1QCBAR)|(1QBBAR&1QDBAR)))}
+    2CLKB={2QAL&2QDBAR}
+    2CLKD={2QAL&(~((2QDBAR&2QCBAR)|(2QBBAR&2QDBAR)))}
U2DLY PINDLY(8,0,5) DPWR DGND
+  1QAL 1QBL 1QCL 1QDL 2QAL 2QBL 2QCL 2QDL
+  1CLKA 1CLKB 2CLK 1CLRBAR 2CLRBAR
+  1QA 1QB 1QC 1QD 2QA 2QB 2QC 2QD
+   IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+      1CK1 = {CHANGED_HL(1CLKA,0)}
+      1CK2 = {CHANGED_HL(1CLKB,0)}
+      2CK = {CHANGED_HL(2CLK,0)}
+      CLR1={CHANGED_HL(1CLRBAR,0)}
+      CLR2={CHANGED_HL(2CLRBAR,0)}
+
+  PINDLY:
+     1QA={
+         CASE(
+            CLR1, DELAY(-1,20ns,30ns),
+            1CK1&TRN_LH, DELAY(-1,7ns,11ns),
+            1CK1&TRN_HL, DELAY(-1,14ns,21ns),
+            DELAY(-1,21ns,31ns))}
+
+     1QB={
+         CASE(
+             CLR1, DELAY(-1,20ns,30ns),
+             1CK2&TRN_LH, DELAY(-1,8ns,12ns),
+             1CK2&TRN_HL, DELAY(-1,12ns,18ns),
+             DELAY(-1,21ns,31ns))}
+
+     1QC={
+         CASE( 
+             CLR1, DELAY(-1,20ns,30ns),
+             1CK2&TRN_LH, DELAY(-1,15ns,23ns),
+             1CK2&TRN_HL, DELAY(-1,21ns,32ns),
+             DELAY(-1,22ns,33ns))}
+
+     1QD={
+         CASE(
+             CLR1, DELAY(-1,20ns,30ns),
+             1CK2&TRN_LH, DELAY(-1,8ns,12ns),
+             1CK2&TRN_HL, DELAY(-1,13ns,20ns),
+             DELAY(-1,21ns,31ns))}
+
+     2QA={
+         CASE(
+             CLR2, DELAY(-1,20ns,30ns),
+             2CK&TRN_LH, DELAY(-1,7ns,11ns),
+             2CK&TRN_HL, DELAY(-1,14ns,21ns),
+             DELAY(-1,21ns,31ns))}
+
+     2QB={
+         CASE(
+             CLR2, DELAY(-1,20ns,30ns),
+             2CK&TRN_LH, DELAY(-1,16ns,24ns),
+             2CK&TRN_HL, DELAY(-1,19ns,29ns),
+             DELAY(-1,21ns,31ns))}
+
+     2QC={
+         CASE(
+             CLR2, DELAY(-1,20ns,30ns),
+             2CK&TRN_LH, DELAY(-1,23ns,35ns),
+             2CK&TRN_HL, DELAY(-1,27ns,40ns),
+             DELAY(-1,28ns,41ns))}
+
+     2QD={
+         CASE(
+             CLR2, DELAY(-1,20ns,30ns),
+             2CK&TRN_LH, DELAY(-1,16ns,24ns),
+             2CK&TRN_HL, DELAY(-1,19ns,29ns),
+             DELAY(-1,21ns,31ns))}
U3CON CONSTRAINT(5) DPWR DGND
+  1CLKA 1CLKB 2CLK 1CLRBAR 2CLRBAR
+  IO_LS IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=1CLKA
+     MAXFREQ=50MEG
+
+  FREQ:
+     NODE=1CLKB
+     MAXFREQ=20MEG
+
+  FREQ:
+     NODE=2CLK
+     MAXFREQ=40MEG
+
+  WIDTH:
+     NODE=1CLKA
+     MIN_HI=10ns
+     MIN_LO=10ns
+
+  WIDTH:
+     NODE=1CLKB
+     MIN_HI=25ns
+     MIN_LO=25ns
+
+  WIDTH:
+     NODE=2CLK
+     MIN_HI=13ns
+     MIN_LO=13ns
+
+  WIDTH:
+     NODE=1CLRBAR
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=2CLRBAR
+     MIN_LO=15ns
+
+  SETUP_HOLD:
+     DATA(1)=1CLRBAR
+     CLOCK HL=1CLKA
+     SETUPTIME_HI=25ns
+   
+  SETUP_HOLD:
+     DATA(1)=1CLRBAR
+     CLOCK HL=1CLKB
+     SETUPTIME_HI=25ns
+   
+  SETUP_HOLD:
+     DATA(1)=2CLRBAR
+     CLOCK HL=2CLK
+     SETUPTIME_HI=25ns
.ENDS 74LS68   


.SUBCKT 74LS69 1CLKA 1CLRBAR 1CLKB 2CLRBAR 2CLK
+     1QA 1QB 1QC 1QD 2QA 2QB 2QC 2QD
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1J JKFF(1) DPWR DGND
+ $D_HI 1CLRBAR 1CLKA $D_HI $D_HI 1QAL $D_NC
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2J JKFF(1) DPWR DGND
+ $D_HI 1CLRBAR 1CLKB $D_HI $D_HI 1QBL $D_NC
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3J JKFF(1) DPWR DGND
+ $D_HI 1CLRBAR 1QBL $D_HI $D_HI 1QCL $D_NC
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4J JKFF(1) DPWR DGND
+ $D_HI 1CLRBAR 1QCL $D_HI $D_HI 1QDL $D_NC
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5J JKFF(1) DPWR DGND
+ $D_HI 2CLRBAR 2CLK $D_HI $D_HI 2QAL $D_NC
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6J JKFF(1) DPWR DGND
+ $D_HI 2CLRBAR 2QAL $D_HI $D_HI 2QBL $D_NC
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U7J JKFF(1) DPWR DGND
+ $D_HI 2CLRBAR 2QBL $D_HI $D_HI 2QCL $D_NC
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U8J JKFF(1) DPWR DGND
+ $D_HI 2CLRBAR 2QCL $D_HI $D_HI 2QDL $D_NC
+ D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(8,0,5) DPWR DGND
+  1QAL 1QBL 1QCL 1QDL 2QAL 2QBL 2QCL 2QDL
+  1CLKA 1CLKB 2CLK 1CLRBAR 2CLRBAR
+  1QA 1QB 1QC 1QD 2QA 2QB 2QC 2QD
+  IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+      1CK1 = {CHANGED_HL(1CLKA,0)}
+      1CK2 = {CHANGED_HL(1CLKB,0)}
+      2CK = {CHANGED_HL(2CLK,0)}
+      CLR1={CHANGED_HL(1CLRBAR,0)}
+      CLR2={CHANGED_HL(2CLRBAR,0)}
+
+  PINDLY:
+     1QA={
+         CASE(
+            CLR1, DELAY(-1,20ns,30ns),
+            1CK1&TRN_LH, DELAY(-1,7ns,11ns),
+            1CK1&TRN_HL, DELAY(-1,14ns,21ns),
+            DELAY(-1,21ns,31ns))}
+
+     1QB={
+         CASE(
+             CLR1, DELAY(-1,20ns,30ns),
+             1CK2&TRN_LH, DELAY(-1,7ns,11ns),
+             1CK2&TRN_HL, DELAY(-1,14ns,21ns),
+             DELAY(-1,21ns,31ns))}
+
+     1QC={
+         CASE( 
+             CLR1, DELAY(-1,20ns,30ns),
+             1CK2&TRN_LH, DELAY(-1,16ns,24ns),
+             1CK2&TRN_HL, DELAY(-1,21ns,32ns),
+             DELAY(-1,22ns,33ns))}
+
+     1QD={
+         CASE(
+             CLR1, DELAY(-1,20ns,30ns),
+             1CK2&TRN_LH, DELAY(-1,25ns,38ns),
+             1CK2&TRN_HL, DELAY(-1,30ns,45ns),
+             DELAY(-1,31ns,46ns))}
+
+     2QA={
+         CASE(
+             CLR2, DELAY(-1,20ns,30ns),
+             2CK&TRN_LH, DELAY(-1,7ns,11ns),
+             2CK&TRN_HL, DELAY(-1,14ns,21ns),
+             DELAY(-1,21ns,31ns))}
+
+     2QB={
+         CASE(
+             CLR2, DELAY(-1,20ns,30ns),
+             2CK&TRN_LH, DELAY(-1,14ns,21ns),
+             2CK&TRN_HL, DELAY(-1,19ns,29ns),
+             DELAY(-1,21ns,31ns))}
+
+     2QC={
+         CASE(
+             CLR2, DELAY(-1,20ns,30ns),
+             2CK&TRN_LH, DELAY(-1,23ns,35ns),
+             2CK&TRN_HL, DELAY(-1,27ns,40ns),
+             DELAY(-1,28ns,41ns))}
+
+     2QD={
+         CASE(
+             CLR2, DELAY(-1,20ns,30ns),
+             2CK&TRN_LH, DELAY(-1,32ns,48ns),
+             2CK&TRN_HL, DELAY(-1,36ns,54ns),
+             DELAY(-1,37ns,55ns))}
U3CON CONSTRAINT(5) DPWR DGND
+  1CLKA 1CLKB 2CLK 1CLRBAR 2CLRBAR
+  IO_LS IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=1CLKA
+     MAXFREQ=50MEG
+
+  FREQ:
+     NODE=1CLKB
+     MAXFREQ=25MEG
+
+  FREQ:
+     NODE=2CLK
+     MAXFREQ=50MEG
+
+  WIDTH:
+     NODE=1CLKA
+     MIN_HI=10ns
+     MIN_LO=10ns
+
+  WIDTH:
+     NODE=1CLKB
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=2CLK
+     MIN_HI=10ns
+     MIN_LO=10ns
+
+  WIDTH:
+     NODE=1CLRBAR
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=2CLRBAR
+     MIN_LO=15ns
+
+  SETUP_HOLD:
+     DATA(1)=1CLRBAR
+     CLOCK HL=1CLKA
+     SETUPTIME_HI=25ns
+   
+  SETUP_HOLD:
+     DATA(1)=1CLRBAR
+     CLOCK HL=1CLKB
+     SETUPTIME_HI=25ns
+   
+  SETUP_HOLD:
+     DATA(1)=2CLRBAR
+     CLOCK HL=2CLK
+     SETUPTIME_HI=25ns
.ENDS 74LS69   


.SUBCKT 7470 PREBAR CLRBAR CLK J1 J2 JBAR
+     K1 K2 KBAR Q QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 anda(3,2) DPWR DGND
+     J1 J2 JB K1 K2 KB J K
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 inva(3) DPWR DGND
+     CLK JBAR KBAR CLKBAR JB KB
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     PREBAR CLRBAR CLKBAR J K Q QBAR
+     DLY_70 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_70 ueff(tppcqlhMX=50ns tppcqhlMX=50ns twpclMN=25ns tpclkqlhTY=27ns
+                 tpclkqlhMX=50ns tpclkqhlTY=18ns tpclkqhlMX=50ns twclklMN=30ns
+                 twclkhMN=20ns tsudclkMN=20ns thdclkMN=5ns)
.ENDS 7470


.SUBCKT 74H71 PREBAR CLK J1A J1B J2A J2B
+     K1A K1B K2A K2B Q QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 SRFF(1) DPWR DGND
+     PREBAR $D_HI CLK MJ MK SJ SK
+     D0_GFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 SRFF(1) DPWR DGND
+     PREBAR $D_HI CLKBAR SJ SK Q_O QBAR_O
+     D0_GFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3LOG LOGICEXP(11,3) DPWR DGND
+     CLK J1A J1B J2A J2B K1A K1B K2A K2B Q_O QBAR_O
+     MJ MK CLKBAR
+     D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   LOGIC:
+     CLKBAR={~CLK}
+     j={(J1A & J1B) | (J2A & J2B)}
+     k={(K1A & K1B) | (K2A & K2B)}
+     jbar={~j}
+     kbar={~k}
+     MJ={(j & k & QBAR_O) | (j & kbar)}
+     MK={(j & k & Q_O) | (jbar & k)}
U4DLY PINDLY(2,0,1) DPWR DGND
+     Q_O QBAR_O
+     PREBAR
+     Q QBAR
+     IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   PINDLY:
+     Q={
+        CASE(
+           CHANGED_HL(PREBAR,0)&TRN_LH, DELAY(-1,6ns,13ns),
+           TRN_LH, DELAY(-1,14ns,21ns),
+           TRN_HL, DELAY(-1,22ns,27ns),
+           DELAY(-1,23ns,28ns))}
+     QBAR={
+         CASE(
+           CHANGED_HL(PREBAR,0)&TRN_HL, DELAY(-1,12ns,24ns),
+           TRN_LH, DELAY(-1,14ns,21ns),
+           TRN_HL, DELAY(-1,22ns,27ns),
+           DELAY(-1,23ns,28ns))}
U5CON CONSTRAINT(2) DPWR DGND
+     CLK PREBAR
+     IO_H IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=12ns
+     MIN_LO=28ns
+
+  WIDTH:
+     NODE=PREBAR
+     MIN_LO=16ns
.ENDS 74H71


.SUBCKT 7472 PREBAR CLRBAR CLK J1 J2 J3 K1 K2 K3 Q QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 SRFF(1) DPWR DGND
+     PREBAR CLRBAR CLK MJ MK SJ SK
+     D0_GFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 SRFF(1) DPWR DGND
+     PREBAR CLRBAR CLKBAR SJ SK Q_O QBAR_O
+     D0_GFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3LOG LOGICEXP(9,3) DPWR DGND
+     CLK J1 J2 J3 K1 K2 K3 Q_O QBAR_O
+     MJ MK CLKBAR
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   LOGIC:
+     CLKBAR={~CLK}
+     j={(J1 & J2 & J3)}
+     k={(K1 & K2 & K3)}
+     jbar={~j}
+     kbar={~k}
+     MJ={(j & k & QBAR_O) | (j & kbar)}
+     MK={(j & k & Q_O) | (jbar & k)}
U4DLY PINDLY(2,0,0) DPWR DGND
+     Q_O QBAR_O
+     Q QBAR
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   PINDLY:
+     Q={
+        CASE(
+           TRN_LH, DELAY(-1,16ns,25ns),
+           TRN_HL, DELAY(-1,25ns,40ns),
+           DELAY(-1,26ns,41ns))}
+     QBAR={
+         CASE(
+           TRN_LH, DELAY(-1,16ns,25ns),
+           TRN_HL, DELAY(-1,25ns,40ns),
+           DELAY(-1,26ns,41ns))}
U5CON CONSTRAINT(3) DPWR DGND
+     CLK PREBAR CLRBAR
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=20ns
+     MIN_LO=47ns
+
+  WIDTH:
+     NODE=PREBAR
+     MIN_LO=25ns
+
+  WIDTH:
+     NODE=CLRBAR
+     MIN_LO=25ns
.ENDS 7472


.SUBCKT 74H72 PREBAR CLRBAR CLK J1 J2 J3 K1 K2 K3 Q QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 SRFF(1) DPWR DGND
+     PREBAR CLRBAR CLK MJ MK SJ SK
+     D0_GFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 SRFF(1) DPWR DGND
+     PREBAR CLRBAR CLKBAR SJ SK Q_O QBAR_O
+     D0_GFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3LOG LOGICEXP(9,3) DPWR DGND
+     CLK J1 J2 J3 K1 K2 K3 Q_O QBAR_O
+     MJ MK CLKBAR
+     D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   LOGIC:
+     CLKBAR={~CLK}
+     j={(J1 & J2 & J3)}
+     k={(K1 & K2 & K3)}
+     jbar={~j}
+     kbar={~k}
+     MJ={(j & k & QBAR_O) | (j & kbar)}
+     MK={(j & k & Q_O) | (jbar & k)}
U4DLY PINDLY(2,0,2) DPWR DGND
+     Q_O QBAR_O
+     PREBAR CLRBAR
+     Q QBAR
+     IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   PINDLY:
+     Q={
+        CASE(
+           CHANGED_HL(PREBAR,0) & TRN_LH, DELAY(-1,6ns,13ns),
+           CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(-1,12ns,24ns),
+           TRN_LH, DELAY(-1,14ns,21ns),
+           TRN_HL, DELAY(-1,22ns,27ns),
+           DELAY(-1,26ns,41ns))}
+     QBAR={
+         CASE(
+           CHANGED_HL(PREBAR,0) & TRN_HL, DELAY(-1,12ns,24ns),
+           CHANGED_HL(CLRBAR,0) & TRN_LH, DELAY(-1,6ns,13ns),
+           TRN_LH, DELAY(-1,14ns,21ns),
+           TRN_HL, DELAY(-1,22ns,27ns),
+           DELAY(-1,26ns,41ns))}
U5CON CONSTRAINT(3) DPWR DGND
+     CLK PREBAR CLRBAR
+     IO_H IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=12ns
+     MIN_LO=28ns
+
+  WIDTH:
+     NODE=PREBAR
+     MIN_LO=16ns
+
+  WIDTH:
+     NODE=CLRBAR
+     MIN_LO=16ns
.ENDS 74H72


.SUBCKT 7473 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 SRFF(1) DPWR DGND
+     $D_HI 1CLRBAR 1CLK MJ MK SJ SK
+     D0_GFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 SRFF(1) DPWR DGND
+     $D_HI 1CLRBAR CLKBAR SJ SK 1Q_O 1QBAR_O
+     D0_GFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3LOG LOGICEXP(5,3) DPWR DGND
+     1CLK 1J 1K 1Q_O 1QBAR_O
+     MJ MK CLKBAR
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   LOGIC:
+     CLKBAR={~1CLK}
+     jbar={~1J}
+     kbar={~1K}
+     MJ={(1J & 1K & 1QBAR_O) | (1J & kbar)}
+     MK={(1J & 1K & 1Q_O) | (jbar & 1K)}
U4DLY PINDLY(2,0,0) DPWR DGND
+     1Q_O 1QBAR_O
+     1Q 1QBAR
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   PINDLY:
+     1Q={
+        CASE(
+           TRN_LH, DELAY(-1,16ns,25ns),
+           TRN_HL, DELAY(-1,25ns,40ns),
+           DELAY(-1,26ns,41ns))}
+     1QBAR={
+         CASE(
+           TRN_LH, DELAY(-1,16ns,25ns),
+           TRN_HL, DELAY(-1,25ns,40ns),
+           DELAY(-1,26ns,41ns))}
U5CON CONSTRAINT(2) DPWR DGND
+     1CLK 1CLRBAR
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=1CLK
+     MIN_HI=20ns
+     MIN_LO=47ns
+
+  WIDTH:
+     NODE=1CLRBAR
+     MIN_LO=25ns
.ENDS 7473


.SUBCKT 74H73 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 SRFF(1) DPWR DGND
+     $D_HI 1CLRBAR 1CLK MJ MK SJ SK
+     D0_GFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 SRFF(1) DPWR DGND
+     $D_HI 1CLRBAR CLKBAR SJ SK 1Q_O 1QBAR_O
+     D0_GFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3LOG LOGICEXP(5,3) DPWR DGND
+     1CLK 1J 1K 1Q_O 1QBAR_O
+     MJ MK CLKBAR
+     D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   LOGIC:
+     CLKBAR={~1CLK}
+     jbar={~1J}
+     kbar={~1K}
+     MJ={(1J & 1K & 1QBAR_O) | (1J & kbar)}
+     MK={(1J & 1K & 1Q_O) | (jbar & 1K)}
U4DLY PINDLY(2,0,1) DPWR DGND
+     1Q_O 1QBAR_O
+     1CLRBAR
+     1Q 1QBAR
+     IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   PINDLY:
+     1Q={
+        CASE(
+           CHANGED_HL(1CLRBAR,0) & TRN_HL, DELAY(-1,12ns,24ns),
+           TRN_LH, DELAY(-1,14ns,21ns),
+           TRN_HL, DELAY(-1,22ns,27ns),
+           DELAY(-1,23ns,28ns))}
+     1QBAR={
+         CASE(
+           CHANGED_HL(1CLRBAR,0) & TRN_LH, DELAY(-1,6ns,13ns),
+           TRN_LH, DELAY(-1,14ns,21ns),
+           TRN_HL, DELAY(-1,22ns,27ns),
+           DELAY(-1,23ns,28ns))}
U5CON CONSTRAINT(2) DPWR DGND
+     1CLK 1CLRBAR
+     IO_H IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=1CLK
+     MIN_HI=12ns
+     MIN_LO=28ns
+
+  WIDTH:
+     NODE=1CLRBAR
+     MIN_LO=16ns
.ENDS 74H73


.SUBCKT 74HC73 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     $D_HI 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     DLY_HC73 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC73 ueff(tppcqlhTY=16ns tppcqlhMX=31ns tppcqhlTY=16ns
+                   tppcqhlMX=31ns twpclMN=20ns tpclkqlhTY=13ns
+                   tpclkqlhMX=25ns tpclkqhlTY=13ns tpclkqhlMX=25ns
+                   twclklMN=20ns twclkhMN=20ns tsudclkMN=30ns
+                   tsupcclkhMN=30ns)
.ENDS 74HC73


.SUBCKT 74HCT73 1J 1K 1CPBAR 1RBAR 1Q 1QBAR
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
UBUF BUF DPWR DGND
+ 1CPBAR 1CPBARST
+ D0_GATE IO_HCT_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U1 JKFF(1) DPWR DGND
+ $D_HI 1RBAR 1CPBARST
+ 1J 1K 1QO 1QBARO
+ D0_EFF IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(2,0,2) DPWR DGND
+ 1QO 1QBARO
+ 1RBAR 1CPBAR
+ 1Q 1QBAR
+ IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+    ASYNCH = {CHANGED(1RBAR,0)}
+    EDGE = {CHANGED_HL(1CPBAR,0)}
+ PINDLY:
+    1Q 1QBAR = {
+      CASE(
+        ASYNCH & TRN_LH, DELAY(-1,18NS,29NS),
+        ASYNCH & TRN_HL, DELAY(-1,18NS,29NS),
+        EDGE & TRN_LH, DELAY(-1,19NS,32NS),
+        EDGE & TRN_HL, DELAY(-1,19NS,32NS),
+        DELAY(-1,20NS,33NS))}
U3 CONSTRAINT(4) DPWR DGND
+ 1CPBAR 1RBAR 1J 1K 
+ IO_HCT IO_LEVEL={IO_LEVEL}
+ FREQ:
+  NODE = 1CPBAR
+  MAXFREQ = 70MEG
+ WIDTH:
+   NODE = 1CPBAR
+   MIN_HI = 8NS
+   MIN_LO = 8NS
+ WIDTH:
+   NODE = 1RBAR
+   MIN_LO = 8NS
+   MIN_HI = 8NS
+ SETUP_HOLD:
+   CLOCK HL = 1CPBAR
+   DATA(2) = 1J 1K
+   SETUPTIME = 8NS
+ SETUP_HOLD:
+   CLOCK HL = 1CPBAR
+   DATA(1) = 1RBAR
+   SETUPTIME_HI = 8NS
.ENDS 74HCT73


.SUBCKT 74LS73A 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     $D_HI 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     DLY_LS73 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS73 ueff(tppcqlhTY=15ns tppcqlhMX=20ns tppcqhlTY=15ns
+                   tppcqhlMX=20ns twpclMN=20ns tpclkqlhTY=15ns
+                   tpclkqlhMX=20ns tpclkqhlTY=15ns tpclkqhlMX=20ns
+                   twclkhMN=20ns tsudclkMN=20ns tsupcclkhMN=20ns)
.ENDS 74LS73A


.SUBCKT 7474 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     DLY_74 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_74 ueff(tppcqlhMX=25ns tppcqhlMX=40ns twpclMN=30ns
+                 tpclkqlhTY=14ns tpclkqlhMX=25ns tpclkqhlTY=20ns
+                 tpclkqhlMX=40ns twclkhMN=30ns twclklMN=37ns
+                 tsudclkMN=20ns thdclkMN=5ns)
.ENDS 7474


.SUBCKT 74AC74 SD1BAR CD1BAR CP1 D1 Q1 Q1BAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+     SD1BAR CD1BAR CP1 D1 Q1 Q1BAR
+     DLY_AC74 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AC74 ueff(tppcqlhMN=3.5ns tppcqlhTY=6ns tppcqlhMX=9ns
+                 tppcqhlMN=3ns tppcqhlTY=8ns tppcqhlMX=9.5ns
+                 twpclMN=4.5ns tpclkqlhMN=3.5ns tpclkqlhTY=6ns
+                 tpclkqlhMX=10ns tpclkqhlMN=2.5ns tpclkqhlTY=6ns
+                 tpclkqhlMX=10ns twclkhMN=4.5ns twclklMN=4.5ns
+                 tsudclkMN=3ns thdclkMN=.5ns)
.ENDS 74AC74


.SUBCKT 74ACT74 SD1BAR CD1BAR CP1 D1 Q1 Q1BAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+     SD1BAR CD1BAR CP1 D1 Q1 Q1BAR
+     DLY_ACT74 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT74 ueff(tppcqlhMN=3ns tppcqlhTY=5.5ns tppcqlhMX=9.5ns
+                 tppcqhlMN=3ns tppcqhlTY=6ns tppcqhlMX=10ns
+                 twpclMN=5ns tpclkqlhMN=4ns tpclkqlhTY=7.5ns
+                 tpclkqlhMX=11ns tpclkqhlMN=3.5ns tpclkqhlTY=6ns
+                 tpclkqhlMX=10ns twclkhMN=5ns twclklMN=5ns
+                 tsudclkMN=3ns thdclkMN=1ns)
.ENDS 74ACT74


.SUBCKT 74ALS74 1PREBAR 1CLK 1D 1CLRBAR 1Q 1QBAR
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+ 1PREBAR 1CLRBAR 1CLK
+ 1D 1QO 1QBARO
+ D0_EFF IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(2,0,3) DPWR DGND
+ 1QO 1QBARO
+ 1PREBAR 1CLRBAR 1CLK
+ 1Q 1QBAR
+ IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+    ASYNCH = {CHANGED(1PREBAR,0) | CHANGED(1CLRBAR,0)}
+    EDGE = {CHANGED_LH(1CLK,0)}
+ PINDLY:
+    1Q 1QBAR = {
+      CASE(
+        ASYNCH & TRN_LH, DELAY(-1,6NS,-1),
+        ASYNCH & TRN_HL, DELAY(-1,10NS,-1),
+        EDGE & TRN_LH, DELAY(-1,8NS,-1),
+        EDGE & TRN_HL, DELAY(-1,12NS,-1),
+        DELAY(-1,13NS,-1))}
U3 CONSTRAINT(4) DPWR DGND
+ 1D 1PREBAR 1CLRBAR 1CLK
+ IO_ALS00 IO_LEVEL={IO_LEVEL}
+ FREQ:
+  NODE = 1CLK
+  MAXFREQ = 34MEG
+ WIDTH:
+   NODE = 1CLK
+   MIN_HI = 12NS
+   MIN_LO = 17NS
+ WIDTH:
+   NODE = 1PREBAR
+   MIN_LO = 15NS
+ WIDTH:
+   NODE = 1CLRBAR
+   MIN_LO = 15NS
+ SETUP_HOLD:
+   CLOCK LH = 1CLK
+   DATA(1) = 1D
+   SETUPTIME = 15NS
+ SETUP_HOLD:
+   CLOCK LH = 1CLK
+   DATA(2) = 1PREBAR 1CLRBAR
+   SETUPTIME_HI = 10NS
.ENDS 74ALS74


.SUBCKT 74ALS74A 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     DLY_ALS74 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS74 ueff(tppcqlhMN=3ns tppcqlhMX=13ns tppcqhlMN=5ns
+                 tppcqhlMX=15ns twpclMN=15ns tpclkqlhMN=5ns
+                 tpclkqlhMX=16ns tpclkqhlMN=5ns tpclkqhlMX=18ns
+                 twclkhMN=14.5ns twclklMN=14.5ns tsudclkMN=15ns
+                 tsupcclkhMN=10ns)
.ENDS 74ALS74A


.SUBCKT 74AS74 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     DLY_AS74 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS74 ueff(tppcqlhMN=3ns tppcqlhMX=7.5ns tppcqhlMN=3.5ns
+                 tppcqhlMX=10.5ns twpclMN=4ns tpclkqlhMN=3.5ns
+                 tpclkqlhMX=8ns tpclkqhlMN=4.5ns tpclkqhlMX=9ns
+                 twclkhMN=4ns twclklMN=5.5ns tsudclkMN=4.5ns
+                 tsupcclkhMN=2ns)
.ENDS 74AS74


.SUBCKT 74F74 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     DLY_F74 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2CON CONSTRAINT(4) DPWR DGND
+     1D 1CLK 1PREBAR 1CLRBAR
+     IO_F IO_LEVEL={IO_LEVEL}
+
+  SETUP_HOLD:
+     CLOCK LH=1CLK
+     DATA(1)=1D
+     SETUPTIME_HI=2ns
+     SETUPTIME_LO=3ns
+     HOLDTIME=1ns
+     WHEN={1PREBAR!='0 & 1CLRBAR!='0}
.model DLY_F74 ueff(tppcqlhMN=2.4ns tppcqlhTY=4.2ns tppcqlhMX=6.1ns tppcqhlMN=2.7ns
+                 tppcqhlTY=6.6ns tppcqhlMX=9ns twpclMN=4ns tpclkqlhMN=3ns
+                 tpclkqlhTY=4.9ns tpclkqlhMX=6.8ns tpclkqhlMN=3.6ns tpclkqhlTY=5.8ns 
+                 tpclkqhlMX=8ns twclkhMN=4ns twclklMN=5ns tsupcclkhMN=2ns)
.ENDS 74F74


.SUBCKT 74H74 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     DLY_H74 IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2CON CONSTRAINT(4) DPWR DGND
+     1D 1CLK 1PREBAR 1CLRBAR
+     IO_H IO_LEVEL={IO_LEVEL}
+
+  SETUP_HOLD:
+     CLOCK LH=1CLK
+     DATA(1)=1D
+     SETUPTIME_LO=15ns
+     SETUPTIME_HI=10ns
+     WHEN={1PREBAR!='0 & 1CLRBAR!='0}
.model DLY_H74 ueff(tppcqlhMX=20ns tppcqhlMX=30ns twpclMN=25ns
+                 tpclkqlhTY=8.5ns tpclkqlhMX=15ns tpclkqhlTY=13ns
+                 tpclkqhlMX=20ns twclkhMN=15ns twclklMN=13.5ns
+                 thdclkMN=5ns)
.ENDS 74H74


.SUBCKT 74HC74 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     DLY_HC74 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC74 ueff(tppcqlhTY=20ns tppcqlhMX=46ns tppcqhlTY=20ns
+                 tppcqhlMX=46ns twpclMN=25ns
+                 tpclkqlhTY=20ns tpclkqlhMX=35ns tpclkqhlTY=20ns
+                 tpclkqhlMX=35ns twclkhMN=20ns twclklMN=20ns
+                 tsudclkMN=25ns tsupcclkhMN=6ns)
.ENDS 74HC74


.SUBCKT 74HC74A RESET1 DATA1 CLOCK1 SET1 Q1 Q1BAR
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+ SET1 RESET1 CLOCK1
+ DATA1 Q1O Q1BARO
+ D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(2,0,3) DPWR DGND
+ Q1O Q1BARO
+ SET1 RESET1 CLOCK1
+ Q1 Q1BAR
+ IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+    ASYNCH = {CHANGED(SET1,0) | CHANGED(RESET1,0)}
+    EDGE = {CHANGED_LH(CLOCK1,0)}
+ PINDLY:
+    Q1 Q1BAR = {
+      CASE(
+        ASYNCH & TRN_LH, DELAY(-1,-1,21NS),
+        ASYNCH & TRN_HL, DELAY(-1,-1,21NS),
+        EDGE & TRN_LH, DELAY(-1,-1,20NS),
+        EDGE & TRN_HL, DELAY(-1,-1,20NS),
+        DELAY(-1,-1,22NS))}
U3 CONSTRAINT(4) DPWR DGND
+ DATA1 CLOCK1 SET1 RESET1
+ IO_HC IO_LEVEL={IO_LEVEL}
+ FREQ:
+  NODE = CLOCK1
+  MAXFREQ = 30MEG
+ WIDTH:
+   NODE = CLOCK1
+   MIN_HI = 12NS
+   MIN_LO = 12NS
+ WIDTH:
+   NODE = SET1
+   MIN_HI = 12NS
+   MIN_LO = 12NS
+ WIDTH:
+   NODE = RESET1
+   MIN_HI = 12NS
+   MIN_LO = 12NS
+ SETUP_HOLD:
+   CLOCK LH = CLOCK1
+   DATA(1) = DATA1
+   SETUPTIME = 16NS
+   HOLDTIME = 3NS
+ SETUP_HOLD:
+   CLOCK LH = CLOCK1
+   DATA(2) = SET1 RESET1
+   SETUPTIME_HI = 8NS
.ENDS 74HC74A


.SUBCKT 74HCT74 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     DLY_HCT74 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HCT74 ueff(tppcqlhTY=21ns tppcqlhMX=35ns tppcqhlTY=21ns
+                 tppcqhlMX=35ns twpclMN=20ns
+                 tpclkqlhTY=20ns tpclkqlhMX=28ns tpclkqhlTY=20ns
+                 tpclkqhlMX=28ns twclkhMN=23ns twclklMN=23ns
+                 tsudclkMN=15ns)
.ENDS 74HCT74


.SUBCKT 74HCT74A RESET1 DATA1 CLOCK1 SET1 Q1 Q1BAR
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+ SET1 RESET1 CLOCK1
+ DATA1 Q1O Q1BARO
+ D0_EFF IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(2,0,3) DPWR DGND
+ Q1O Q1BARO
+ SET1 RESET1 CLOCK1
+ Q1 Q1BAR
+ IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+    ASYNCH = {CHANGED(SET1,0) | CHANGED(RESET1,0)}
+    EDGE = {CHANGED_LH(CLOCK1,0)}
+ PINDLY:
+    Q1 Q1BAR = {
+      CASE(
+        ASYNCH & TRN_LH, DELAY(-1,-1,24NS),
+        ASYNCH & TRN_HL, DELAY(-1,-1,24NS),
+        EDGE & TRN_LH, DELAY(-1,-1,24NS),
+        EDGE & TRN_HL, DELAY(-1,-1,24NS),
+        DELAY(-1,-1,25NS))}
U3 CONSTRAINT(4) DPWR DGND
+ DATA1 CLOCK1 SET1 RESET1
+ IO_HCT IO_LEVEL={IO_LEVEL}
+ FREQ:
+  NODE = CLOCK1
+  MAXFREQ = 30MEG
+ WIDTH:
+   NODE = CLOCK1
+   MIN_HI = 15NS
+   MIN_LO = 15NS
+ WIDTH:
+   NODE = SET1
+   MIN_HI = 15NS
+   MIN_LO = 15NS
+ WIDTH:
+   NODE = RESET1
+   MIN_HI = 15NS
+   MIN_LO = 15NS
+ SETUP_HOLD:
+   CLOCK LH = CLOCK1
+   DATA(1) = DATA1
+   SETUPTIME = 15NS
+   HOLDTIME = 3NS
+ SETUP_HOLD:
+   CLOCK LH = CLOCK1
+   DATA(2) = SET1 RESET1
+   SETUPTIME_HI = 6NS
.ENDS 74HCT74A


.SUBCKT 74LS74A 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     DLY_LS74 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS74 ueff(tppcqlhTY=13ns tppcqlhMX=25ns tppcqhlTY=25ns
+                 tppcqhlMX=40ns twpclMN=25ns tpclkqlhTY=13ns
+                 tpclkqlhMX=25ns tpclkqhlTY=25ns tpclkqhlMX=40ns
+                 twclkhMN=25ns tsudclkMN=20ns thdclkMN=5ns)
.ENDS 74LS74A


.SUBCKT 74S74 1PREBAR 1CLRBAR 1CLK 1D 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1D 1Q_O 1QBAR_O
+     DLY_S74 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(2,0,3) DPWR DGND
+     1Q_O 1QBAR_O
+     1PREBAR 1CLRBAR 1CLK
+     1Q 1QBAR
+     IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+      PRE={CHANGED_HL(1PREBAR,0)}
+      CLR={CHANGED_HL(1CLRBAR,0)}
+
+  PINDLY:
+     1Q 1QBAR = {
+         CASE(
+            (PRE | CLR) & 1CLK!='0 & TRN_HL, DELAY(-1,9ns,13.5ns),
+            (PRE | CLR) & 1CLK!='1 & TRN_HL, DELAY(-1,5ns,8ns),
+            (PRE | CLR) & TRN_HL, DELAY(-1,9ns,13.5ns),
+            DELAY(0,0,0))}
.model DLY_S74 ueff(tppcqlhTY=4ns tppcqlhMX=6ns twpclMN=7ns tpclkqlhTY=6ns
+                 tpclkqlhMX=9ns tpclkqhlTY=6ns tpclkqhlMX=9ns
+                 twclkhMN=6ns twclklMN=7.3ns tsudclkMN=3ns thdclkMN=2ns)
.ENDS 74S74


.SUBCKT 7475 C 1D 2D 1Q 1QBAR 2Q 2QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DLTCH(2) DPWR DGND
+     $D_HI $D_HI C 1D 2D 1Q_O 2Q_O 1QBAR_O 2QBAR_O
+     DLY_75 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(4,0,3) DPWR DGND
+     1Q_O 1QBAR_O 2Q_O 2QBAR_O
+     C 1D 2D
+     1Q 1QBAR 2Q 2QBAR
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     DATA={CHANGED(1D,0) | CHANGED(2D,0)}
+     CLK = {CHANGED_LH(C,0)}
+
+  PINDLY:
+     1Q 2Q = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,16ns,30ns),
+           DATA & TRN_HL, DELAY(-1,14ns,25ns),
+           CLK & TRN_LH, DELAY(-1,16ns,30ns),
+           CLK & TRN_HL, DELAY(-1,7ns,15ns),
+           DELAY(-1,17ns,31ns))}
+
+     1QBAR 2QBAR = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,24ns,40ns),
+           DATA & TRN_HL, DELAY(-1,7ns,15ns),
+           CLK & TRN_LH, DELAY(-1,16ns,30ns),
+           CLK & TRN_HL, DELAY(-1,7ns,15ns),
+           DELAY(-1,25ns,41ns))}
.model DLY_75 ugff (twghMN=20ns tsudgMN=20ns thdgMN=5ns)
.ENDS 7475


.SUBCKT 74HC75 C 1D 2D 1Q 1QBAR 2Q 2QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DLTCH(2) DPWR DGND
+     $D_HI $D_HI C 1D 2D 1Q 2Q 1QBAR 2QBAR
+     DLY_HC75 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC75 ugff (twghMN=20ns tsudgMN=25ns thdgMN=5ns
+                             tpgqlhTY=15ns tpgqlhMX=26ns tpgqhlTY=15ns
+                             tpgqhlMX=26ns tpdqlhTY=14ns tpdqlhMX=24ns
+                             tpdqhlTY=14ns tpdqhlMX=24ns)
.ENDS 74HC75


.SUBCKT 74HCT75 1D 2D 1Q 1QBAR 2Q 2QBAR LE1-2
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 DLTCH(2) DPWR DGND
+ $D_HI $D_HI LE1-2
+ 1D 2D 1QO 2QO 1QBARO 2QBARO
+ D0_GFF IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(4,0,3) DPWR DGND
+ 1QO 2QO 1QBARO 2QBARO
+ 1D 2D LE1-2
+ 1Q 2Q 1QBAR 2QBAR
+ IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+    DATA = {CHANGED(1D,0) | CHANGED(2D,0)}
+    LATCH = {CHANGED(LE1-2,0)}
+ PINDLY:
+    1Q 2Q = {
+      CASE(
+        LATCH & (TRN_LH | TRN_HL), DELAY(-1,13NS,28NS),
+        DATA & (TRN_LH | TRN_HL), DELAY(-1,15NS,28NS),
+        DELAY(-1,16NS,29NS))}
+    1QBAR 2QBAR = {
+      CASE(
+        LATCH & (TRN_LH | TRN_HL), DELAY(-1,15NS,30NS),
+        DATA & (TRN_LH | TRN_HL), DELAY(-1,15NS,28NS),
+        DELAY(-1,16NS,29NS))}
U3 CONSTRAINT(3) DPWR DGND
+ 1D 2D LE1-2
+ IO_HCT IO_LEVEL={IO_LEVEL}
+ WIDTH:
+   NODE = LE1-2
+   MIN_HI = 4NS
+ SETUP_HOLD:
+   CLOCK HL = LE1-2
+   DATA(2) = 1D 2D
+   SETUPTIME = 4NS
.ENDS 74HCT75


.SUBCKT 74LS75 C 1D 2D 1Q 1QBAR 2Q 2QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DLTCH(2) DPWR DGND
+     $D_HI $D_HI C 1D 2D 1Q_O 2Q_O 1QBAR_O 2QBAR_O
+     DLY_LS75 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(4,0,3) DPWR DGND
+     1Q_O 1QBAR_O 2Q_O 2QBAR_O
+     C 1D 2D
+     1Q 1QBAR 2Q 2QBAR
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     DATA={CHANGED(1D,0) | CHANGED(2D,0)}
+     CLK = {CHANGED_LH(C,0)}
+
+  PINDLY:
+     1Q 2Q = {
+        CASE(
+           CLK & TRN_LH, DELAY(-1,15ns,27ns),
+           CLK & TRN_HL, DELAY(-1,14ns,25ns),
+           DATA & TRN_LH, DELAY(-1,15ns,27ns),
+           DATA & TRN_HL, DELAY(-1,9ns,17ns),
+           DELAY(-1,16ns,28ns))}
+
+     1QBAR 2QBAR = {
+        CASE(
+           CLK & TRN_LH, DELAY(-1,16ns,30ns),
+           CLK & TRN_HL, DELAY(-1,7ns,15ns),
+           DATA & TRN_LH, DELAY(-1,12ns,20ns),
+           DATA & TRN_HL, DELAY(-1,7ns,15ns),
+           DELAY(-1,17ns,31ns))}
.model DLY_LS75 ugff (twghMN=20ns tsudgMN=20ns thdgMN=5ns)
.ENDS 74LS75


.SUBCKT 7476 1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 SRFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK MJ MK SJ SK
+     D0_GFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 SRFF(1) DPWR DGND
+     1PREBAR 1CLRBAR CLKBAR SJ SK 1Q_O 1QBAR_O
+     D0_GFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3LOG LOGICEXP(5,3) DPWR DGND
+     1CLK 1J 1K 1Q_O 1QBAR_O
+     MJ MK CLKBAR
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   LOGIC:
+     CLKBAR={~1CLK}
+     jbar={~1J}
+     kbar={~1K}
+     MJ={(1J & 1K & 1QBAR_O) | (1J & kbar)}
+     MK={(1J & 1K & 1Q_O) | (jbar & 1K)}
U4DLY PINDLY(2,0,0) DPWR DGND
+     1Q_O 1QBAR_O
+     1Q 1QBAR
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   PINDLY:
+     1Q={
+        CASE(
+           TRN_LH, DELAY(-1,16ns,25ns),
+           TRN_HL, DELAY(-1,25ns,40ns),
+           DELAY(-1,26ns,41ns))}
+     1QBAR={
+         CASE(
+           TRN_LH, DELAY(-1,16ns,25ns),
+           TRN_HL, DELAY(-1,25ns,40ns),
+           DELAY(-1,26ns,41ns))}
U5CON CONSTRAINT(3) DPWR DGND
+     1CLK 1CLRBAR 1PREBAR
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=1CLK
+     MIN_HI=20ns
+     MIN_LO=47ns
+
+  WIDTH:
+     NODE=1CLRBAR
+     MIN_LO=25ns
+
+  WIDTH:
+     NODE=1PREBAR
+     MIN_LO=25ns
.ENDS 7476


.SUBCKT 74H76 1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 SRFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK MJ MK SJ SK
+     D0_GFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 SRFF(1) DPWR DGND
+     1PREBAR 1CLRBAR CLKBAR SJ SK 1Q_O 1QBAR_O
+     D0_GFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3LOG LOGICEXP(5,3) DPWR DGND
+     1CLK 1J 1K 1Q_O 1QBAR_O
+     MJ MK CLKBAR
+     D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   LOGIC:
+     CLKBAR={~1CLK}
+     jbar={~1J}
+     kbar={~1K}
+     MJ={(1J & 1K & 1QBAR_O) | (1J & kbar)}
+     MK={(1J & 1K & 1Q_O) | (jbar & 1K)}
U4DLY PINDLY(2,0,2) DPWR DGND
+     1Q_O 1QBAR_O
+     1PREBAR 1CLRBAR
+     1Q 1QBAR
+     IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     PCL={CHANGED_HL(1PREBAR,0) | CHANGED_HL(1CLRBAR,0)}
+
+  PINDLY:
+     1Q={
+        CASE(
+           PCL & TRN_LH, DELAY(-1,6ns,13ns),
+           PCL & TRN_HL, DELAY(-1,12ns,24ns),
+           TRN_LH, DELAY(-1,14ns,21ns),
+           TRN_HL, DELAY(-1,22ns,27ns),
+           DELAY(-1,23ns,28ns))}
+     1QBAR={
+         CASE(
+           PCL & TRN_LH, DELAY(-1,6ns,13ns),
+           PCL & TRN_HL, DELAY(-1,12ns,24ns),
+           TRN_LH, DELAY(-1,14ns,21ns),
+           TRN_HL, DELAY(-1,22ns,27ns),
+           DELAY(-1,23ns,28ns))}
U5CON CONSTRAINT(3) DPWR DGND
+     1CLK 1CLRBAR 1PREBAR
+     IO_H IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=1CLK
+     MIN_HI=12ns
+     MIN_LO=28ns
+
+  WIDTH:
+     NODE=1CLRBAR
+     MIN_LO=16ns
+
+  WIDTH:
+     NODE=1PREBAR
+     MIN_LO=16ns
.ENDS 74H76


.SUBCKT 74HC76 1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     DLY_HC76 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC76 ueff(tppcqlhTY=16ns tppcqlhMX=31ns tppcqhlTY=16ns
+                   tppcqhlMX=31ns twpclMN=25ns tpclkqlhTY=19ns
+                   tpclkqlhMX=29ns tpclkqhlTY=19ns tpclkqhlMX=29ns
+                   twclklMN=20ns twclkhMN=20ns tsudclkMN=38ns
+                   tsupcclkhMN=25ns)
.ENDS 74HC76


.SUBCKT 74LS76A 1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     DLY_LS76 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2CON CONSTRAINT(3) DPWR DGND
+     1CLRBAR 1PREBAR 1CLK
+     IO_LS IO_LEVEL={IO_LEVEL}
+
+  SETUP_HOLD:
+     CLOCK HL=1CLK
+     DATA(1)=1PREBAR
+     SETUPTIME_HI=25ns
+
+  SETUP_HOLD:
+     CLOCK HL=1CLK
+     DATA(1)=1CLRBAR
+     SETUPTIME_HI=20ns
.model DLY_LS76 ueff(tppcqlhTY=15ns tppcqlhMX=20ns tppcqhlTY=15ns
+                   tppcqhlMX=20ns twpclMN=25ns tpclkqlhTY=15ns
+                   tpclkqlhMX=20ns tpclkqhlTY=15ns tpclkqhlMX=20ns
+                   twclkhMN=20ns tsudclkMN=20ns)
.ENDS 74LS76A


.SUBCKT 74HC77 1D 2D 1Q 2Q 1C_2C
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 DLTCH(2) DPWR DGND
+ $D_HI $D_HI 1C_2C
+ 1D 2D 1QO 2QO $D_NC $D_NC
+ D0_GFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(2,0,3) DPWR DGND
+ 1QO 2QO
+ 1D 2D 1C_2C
+ 1Q 2Q
+ IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+    DATA = {CHANGED(1D,0) | CHANGED(2D,0)}
+    LATCH = {CHANGED(1C_2C,0)}
+ PINDLY:
+    1Q 2Q = {
+      CASE(
+        LATCH & (TRN_LH | TRN_HL), DELAY(-1,14NS,26NS),
+        DATA & (TRN_LH | TRN_HL), DELAY(-1,12NS,24NS),
+        DELAY(-1,15NS,27NS))}
U3 CONSTRAINT(3) DPWR DGND
+ 1D 2D 1C_2C
+ IO_HC IO_LEVEL={IO_LEVEL}
+ WIDTH:
+   NODE = 1C_2C
+   MIN_HI = 16NS
+ SETUP_HOLD:
+   CLOCK HL = 1C_2C
+   DATA(2) = 1D 2D
+   SETUPTIME = 20NS
+   HOLDTIME = 5NS
.ENDS 74HC77


.SUBCKT 74LS77 D0 D1 Q0 Q1 E01
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 DLTCH(2) DPWR DGND
+ $D_HI $D_HI E01
+ D0 D1 Q0O Q1O Q0BARO Q1BARO
+ D0_GFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(2,0,3) DPWR DGND
+ Q0O Q1O
+ D0 D1 E01
+ Q0 Q1
+ IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+    DATA = {CHANGED(D0,0) | CHANGED(D1,0)}
+    LATCH = {CHANGED(E01,0)}
+ PINDLY:
+    Q0 Q1 = {
+      CASE(
+        LATCH & TRN_LH, DELAY(-1,10NS,18NS),
+        LATCH & TRN_HL, DELAY(-1,10NS,18NS),
+        DATA & TRN_LH, DELAY(-1,11NS,19NS),
+        DATA & TRN_HL, DELAY(-1,9NS,17NS),
+        DELAY(-1,12NS,20NS))}
U3 CONSTRAINT(3) DPWR DGND
+ D0 D1 E01
+ IO_LS IO_LEVEL={IO_LEVEL}
+ WIDTH:
+   NODE = E01
+   MIN_HI = 20NS
+ SETUP_HOLD:
+   CLOCK HL = E01
+   DATA(2) = D0 D1
+   SETUPTIME = 20NS
.ENDS 74LS77


.SUBCKT 74H78 CLRBAR CLK 1PREBAR 1J 1K 2PREBAR 2J 2K 1Q 1QBAR 2Q 2QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 SRFF(1) DPWR DGND
+     1PREBAR CLRBAR CLK 1MJ 1MK 1SJ 1SK
+     D0_GFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 SRFF(1) DPWR DGND
+     1PREBAR CLRBAR CLKBAR 1SJ 1SK 1Q_O 1QBAR_O
+     D0_GFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 SRFF(1) DPWR DGND
+     2PREBAR CLRBAR CLK 2MJ 2MK 2SJ 2SK
+     D0_GFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 SRFF(1) DPWR DGND
+     2PREBAR CLRBAR CLKBAR 2SJ 2SK 2Q_O 2QBAR_O
+     D0_GFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3LOG LOGICEXP(9,5) DPWR DGND
+     CLK 1J 1K 2J 2K 1Q_O 1QBAR_O 2Q_O 2QBAR_O
+     1MJ 1MK 2MJ 2MK CLKBAR
+     D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   LOGIC:
+     CLKBAR={~CLK}
+     1jbar={~1J}
+     1kbar={~1K}
+     2jbar={~2J}
+     2kbar={~2K}
+     1MJ={(1J & 1K & 1QBAR_O) | (1J & 1kbar)}
+     1MK={(1J & 1K & 1Q_O) | (1jbar & 1K)}
+     2MJ={(2J & 2K & 2QBAR_O) | (2J & 2kbar)}
+     2MK={(2J & 2K & 2Q_O) | (2jbar & 2K)}
U4DLY PINDLY(4,0,3) DPWR DGND
+     1Q_O 1QBAR_O 2Q_O 2QBAR_O
+     1PREBAR 2PREBAR CLRBAR
+     1Q 1QBAR 2Q 2QBAR
+     IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     PCL1 = {CHANGED_HL(1PREBAR,0) | CHANGED_HL(CLRBAR,0)}
+     PCL2 = {CHANGED_HL(CLRBAR,0) | CHANGED_HL(2PREBAR,0)}
+
+  PINDLY:
+     1Q = {
+        CASE(
+           PCL1 & TRN_LH, DELAY(-1,6ns,13ns),
+           PCL1 & TRN_HL, DELAY(-1,12ns,24ns),
+           TRN_LH, DELAY(-1,14ns,21ns),
+           TRN_HL, DELAY(-1,22ns,27ns),
+           DELAY(-1,23ns,28ns))}
+
+     2Q = {
+        CASE(
+           PCL2 & TRN_LH, DELAY(-1,6ns,13ns),
+           PCL2 & TRN_HL, DELAY(-1,12ns,24ns),
+           TRN_LH, DELAY(-1,14ns,21ns),
+           TRN_HL, DELAY(-1,22ns,27ns),
+           DELAY(-1,23ns,28ns))}
+
+     1QBAR = {
+         CASE(
+           PCL1 & TRN_LH, DELAY(-1,6ns,13ns),
+           PCL1 & TRN_HL, DELAY(-1,12ns,24ns),
+           TRN_LH, DELAY(-1,14ns,21ns),
+           TRN_HL, DELAY(-1,22ns,27ns),
+           DELAY(-1,23ns,28ns))}
+
+     2QBAR = {
+         CASE(
+           PCL2 & TRN_LH, DELAY(-1,6ns,13ns),
+           PCL2 & TRN_HL, DELAY(-1,12ns,24ns),
+           TRN_LH, DELAY(-1,14ns,21ns),
+           TRN_HL, DELAY(-1,22ns,27ns),
+           DELAY(-1,23ns,28ns))}
U5CON CONSTRAINT(4) DPWR DGND
+     CLK CLRBAR 1PREBAR 2PREBAR
+     IO_H IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=12ns
+     MIN_LO=28ns
+
+  WIDTH:
+     NODE=CLRBAR
+     MIN_LO=16ns
+
+  WIDTH:
+     NODE=1PREBAR
+     MIN_LO=16ns
+
+  WIDTH:
+     NODE=2PREBAR
+     MIN_LO=16ns
.ENDS 74H78


.SUBCKT 74HC78 CLRBAR CLK 1PREBAR 1J 1K 2PREBAR 2J 2K 1Q 1QBAR 2Q 2QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR CLRBAR CLK 1J 1K 1Q 1QBAR
+     DLY_HC78 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     2PREBAR CLRBAR CLK 2J 2K 2Q 2QBAR
+     DLY_HC78 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC78 ueff(tppcqlhTY=16ns tppcqlhMX=31ns tppcqhlTY=16ns
+                   tppcqhlMX=31ns twpclMN=20ns tpclkqlhTY=13ns
+                   tpclkqlhMX=25ns tpclkqhlTY=13ns tpclkqhlMX=25ns
+                   twclklMN=20ns twclkhMN=20ns tsudclkMN=30ns
+                   tsupcclkhMN=30ns)
.ENDS 74HC78


.SUBCKT 74LS78A CLRBAR CLK 1PREBAR 1J 1K 2PREBAR 2J 2K 1Q 1QBAR 2Q 2QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR CLRBAR CLK 1J 1K 1Q 1QBAR
+     DLY_LS78 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     2PREBAR CLRBAR CLK 2J 2K 2Q 2QBAR
+     DLY_LS78 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS78 ueff(tppcqlhTY=15ns tppcqlhMX=20ns tppcqhlTY=15ns
+                   tppcqhlMX=20ns twpclMN=25ns tpclkqlhTY=15ns
+                   tpclkqlhMX=20ns tpclkqhlTY=15ns tpclkqhlMX=20ns
+                   twclkhMN=20ns tsudclkMN=20ns tsupcclkhMN=20ns)
.ENDS 74LS78A


.SUBCKT 7482 C0 A1 A2 B1 B2 S1 S2 C2
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(5,3) DPWR DGND
+     C0 A1 A2 B1 B2
+     S1_O S2_O C2_O
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     a2bar = {~A2}
+     b2bar = {~B2}
+     look = {~((C0 & A1) | (C0 & B1) | (A1 & B1))}
+     S1_O = {(C0 & look) | (A1 & look) | (B1 & look) | (C0 & A1 & B1)}
+     C2_O = {~((look & a2bar) | (look & b2bar) | (a2bar & b2bar))}
+     S2_O = {~((look & C2_O) | (a2bar & C2_O) | (b2bar & C2_O) | (look & a2bar & b2bar))}
U2DLY PINDLY(3,0,5) DPWR DGND
+     S1_O S2_O C2_O
+     C0 A1 A2 B1 B2
+     S1 S2 C2
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     DATA = {CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(B1,0) | CHANGED(B2,0)}
+
+  PINDLY:
+     S1 = {
+       CASE(
+          DATA & TRN_LH, DELAY(-1,-1,40ns),
+          CHANGED(C0,0) & TRN_LH, DELAY(-1,-1,34ns),
+          CHANGED(C0,0) & TRN_HL, DELAY(-1,-1,40ns),
+          DATA & TRN_HL, DELAY(-1,-1,35ns),
+          DELAY(-1,-1,41ns))}
+
+     S2 = {
+       CASE(
+          DATA & TRN_LH, DELAY(-1,-1,40ns),
+          CHANGED(C0,0) & TRN_LH, DELAY(-1,-1,38ns),
+          CHANGED(C0,0) & TRN_HL, DELAY(-1,-1,42ns),
+          DATA & TRN_HL, DELAY(-1,-1,35ns),
+          DELAY(-1,-1,43ns))}
+
+     C2 = {
+       CASE(
+          DATA & TRN_LH, DELAY(-1,-1,40ns),
+          DATA & TRN_HL, DELAY(-1,-1,35ns),
+          CHANGED(C0,0) & TRN_LH, DELAY(-1,12ns,19ns),
+          CHANGED(C0,0) & TRN_HL, DELAY(-1,17ns,27ns),
+          DELAY(-1,26ns,41ns))}
.ENDS 7482


.SUBCKT 7483A C0 A1 A2 A3 A4 B1 B2 B3 B4 S1 S2 S3 S4 C4
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(9,5) DPWR DGND
+     C0 A1 A2 A3 A4 B1 B2 B3 B4
+     S1_O S2_O S3_O S4_O C4_O
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     c0bar = {~C0}
+     nor1 = {~(A1 | B1)}
+     nand1 = {~(A1 & B1)}
+     nor2 = {~(A2 | B2)}
+     nand2 = {~(A2 & B2)}
+     nor3 = {~(A3 | B3)}
+     nand3 = {~(A3 & B3)}
+     nor4 = {~(A4 | B4)}
+     nand4 = {~(A4 & B4)}
+     C4_O = {~(nor4 | (nor3 & nand4) | (nor2 & nand4 & nand3) | (nor1 & nand4 & nand3 & 
+             nand2) | (nand4 & nand3 & nand2 & nand1 & c0bar))}
+     S4_O = {(nand4 & (~nor4)) ^ (~(nor3 | (nor2 & nand3) | (nor1 & nand3 & nand2) |
+             (nand3 & nand2 & nand1 & c0bar)))}
+     S3_O = {(nand3 & (~nor3)) ^ (~(nor2 | (nor1 & nand2) | (nand2 & nand1 & c0bar)))}
+     S2_O = {(nand2 & (~nor2)) ^ (~(nor1 | (nand1 & c0bar)))}
+     S1_O = {(nand1 & (~nor1)) ^ C0}
U2DLY PINDLY(5,0,9) DPWR DGND
+     S1_O S2_O S3_O S4_O C4_O
+     C0 A1 A2 A3 A4 B1 B2 B3 B4
+     S1 S2 S3 S4 C4
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     DATA = {CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) |
+                  CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0)}
+     CARRY = {CHANGED(C0,0)}
+
+  PINDLY:
+     S1 S2 S3 S4 = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,16ns,24ns),
+           DATA & TRN_HL, DELAY(-1,16ns,24ns),
+           CARRY & TRN_LH, DELAY(-1,14ns,21ns),
+           CARRY & TRN_HL, DELAY(-1,12ns,21ns),
+           DELAY(-1,17ns,25ns))}
+
+     C4 = {
+        CASE(
+           TRN_LH, DELAY(-1,9ns,14ns),
+           TRN_HL, DELAY(-1,11ns,16ns),
+           DELAY(-1,12ns,17ns))}
.ENDS 7483A


.SUBCKT 74LS83A C0 A1 A2 A3 A4 B1 B2 B3 B4 S1 S2 S3 S4 C4
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(9,5) DPWR DGND
+     C0 A1 A2 A3 A4 B1 B2 B3 B4
+     S1_O S2_O S3_O S4_O C4_O
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     c0bar = {~C0}
+     nor1 = {~(A1 | B1)}
+     nand1 = {~(A1 & B1)}
+     nor2 = {~(A2 | B2)}
+     nand2 = {~(A2 & B2)}
+     nor3 = {~(A3 | B3)}
+     nand3 = {~(A3 & B3)}
+     nor4 = {~(A4 | B4)}
+     nand4 = {~(A4 & B4)}
+     C4_O = {~(nor4 | (nor3 & nand4) | (nor2 & nand4 & nand3) | (nor1 & nand4 & nand3 & 
+             nand2) | (nand4 & nand3 & nand2 & nand1 & c0bar))}
+     S4_O = {(nand4 & (~nor4)) ^ (~(nor3 | (nor2 & nand3) | (nor1 & nand3 & nand2) |
+             (nand3 & nand2 & nand1 & c0bar)))}
+     S3_O = {(nand3 & (~nor3)) ^ (~(nor2 | (nor1 & nand2) | (nand2 & nand1 & c0bar)))}
+     S2_O = {(nand2 & (~nor2)) ^ (~(nor1 | (nand1 & c0bar)))}
+     S1_O = {(nand1 & (~nor1)) ^ C0}
U2DLY PINDLY(5,0,9) DPWR DGND
+     S1_O S2_O S3_O S4_O C4_O
+     C0 A1 A2 A3 A4 B1 B2 B3 B4
+     S1 S2 S3 S4 C4
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     DATA = {CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0) |
+                  CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) | CHANGED(B4,0)}
+     CARRY = {CHANGED(C0,0)}
+
+  PINDLY:
+     S1 S2 S3 S4 = {
+        CASE(
+           CARRY & TRN_LH, DELAY(-1,16ns,24ns),
+           DATA & TRN_LH, DELAY(-1,15ns,24ns),
+           TRN_HL, DELAY(-1,15ns,24ns),
+           DELAY(-1,17ns,25ns))}
+
+     C4 = {
+        CASE(
+           TRN_LH, DELAY(-1,11ns,17ns),
+           CARRY & TRN_HL, DELAY(-1,15ns,22ns),
+           DATA & TRN_HL, DELAY(-1,12ns,17ns),
+           DELAY(-1,16ns,23ns))}
.ENDS 74LS83A


.SUBCKT 7485 A0 A1 A2 A3 ALTBI AEQBI AGTBI B0 B1 B2 B3 ALTBO AEQBO AGTBO
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(11,3) DPWR DGND
+     A0 A1 A2 A3 ALTBI AEQBI AGTBI B0 B1 B2 B3
+     ALTBO_O AEQBO_O AGTBO_O
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     nand3 = {~(A3 & B3)}
+     nand2 = {~(A2 & B2)}
+     nand1 = {~(A1 & B1)}
+     nand0 = {~(A0 & B0)}
+     nor3 = {~((A3 & nand3) | (B3 & nand3))}
+     nor2 = {~((A2 & nand2) | (B2 & nand2))}
+     nor1 = {~((A1 & nand1) | (B1 & nand1))}
+     nor0 = {~((A0 & nand0) | (B0 & nand0))}
+     AGTBO_O = {~((B3 & nand3) | (B2 & nand2 & nor3) | (B1 & nand1 & nor3 & nor2) |
+          (B0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & ALTBI) |
+          (nor3 & nor2 & nor1 & nor0 & AEQBI))}
+     AEQBO_O = {nor3 & nor2 & AEQBI & nor1 & nor0}
+     ALTBO_O = {~((A3 & nand3) | (A2 & nand2 & nor3) | (A1 & nand1 & nor3 & nor2) |
+          (A0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & AGTBI) |
+          (nor3 & nor2 & nor1 & nor0 & AEQBI))}
U2DLY PINDLY(3,0,11) DPWR DGND
+     ALTBO_O AEQBO_O AGTBO_O
+     A0 A1 A2 A3 ALTBI AEQBI AGTBI B0 B1 B2 B3
+     ALTBO AEQBO AGTBO
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     DATA = {CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) |
+                 CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0)}
+     LTHAN = {CHANGED(ALTBI,0)}
+     GTHAN = {CHANGED(AGTBI,0)}
+     EQUAL = {CHANGED(AEQBI,0)}
+
+  PINDLY:
+     AEQBO = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,23ns,35ns),
+           DATA & TRN_HL, DELAY(-1,20ns,30ns),
+           EQUAL & TRN_LH, DELAY(-1,13ns,20ns),
+           EQUAL & TRN_HL, DELAY(-1,11ns,17ns),
+           DELAY(-1,24ns,36ns))}
+
+     ALTBO AGTBO = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,17ns,26ns),
+           DATA & TRN_HL, DELAY(-1,20ns,30ns),
+           (LTHAN | EQUAL | GTHAN) & TRN_LH, DELAY(-1,7ns,11ns),
+           (LTHAN | EQUAL | GTHAN) & TRN_HL, DELAY(-1,11ns,17ns),
+           DELAY(-1,21ns,31ns))}
.ENDS 7485


.SUBCKT 74F85 A0 A1 A2 A3 IALSB IAEQB IAGRB B0 B1 B2 B3 OALSB OAEQB OAGRB
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(11,3) DPWR DGND
+     A0 A1 A2 A3 IALSB IAEQB IAGRB B0 B1 B2 B3
+     OALSB_O OAEQB_O OAGRB_O
+     D0_GATE IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     nand3 = {~(A3 & B3)}
+     nand2 = {~(A2 & B2)}
+     nand1 = {~(A1 & B1)}
+     nand0 = {~(A0 & B0)}
+     nor3 = {~((A3 & nand3) | (B3 & nand3))}
+     nor2 = {~((A2 & nand2) | (B2 & nand2))}
+     nor1 = {~((A1 & nand1) | (B1 & nand1))}
+     nor0 = {~((A0 & nand0) | (B0 & nand0))}
+     OAGRB_O = {~((B3 & nand3) | (B2 & nand2 & nor3) | (B1 & nand1 & nor3 & nor2) |
+          (B0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & IALSB) |
+          (nor3 & nor2 & nor1 & nor0 & IAEQB))}
+     OAEQB_O = {nor3 & nor2 & IAEQB & nor1 & nor0}
+     OALSB_O = {~((A3 & nand3) | (A2 & nand2 & nor3) | (A1 & nand1 & nor3 & nor2) |
+          (A0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & IAGRB) |
+          (nor3 & nor2 & nor1 & nor0 & IAEQB))}
U2DLY PINDLY(3,0,11) DPWR DGND
+     OALSB_O OAEQB_O OAGRB_O
+     A0 A1 A2 A3 IALSB IAEQB IAGRB B0 B1 B2 B3
+     OALSB OAEQB OAGRB
+     IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     DATA = {CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) |
+                 CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0)}
+     LTHAN = {CHANGED(IALSB,0)}
+     GTHAN = {CHANGED(IAGRB,0)}
+     EQUAL = {CHANGED(IAEQB,0)}
+
+  PINDLY:
+     OAEQB = {
+        CASE(
+           DATA & TRN_LH, DELAY(5.5NS,-1,11.5ns),
+           DATA & TRN_HL, DELAY(7NS,-1,14ns),
+           EQUAL & TRN_LH, DELAY(2.5NS,-1,7ns),
+           EQUAL & TRN_HL, DELAY(3.5NS,-1,10ns),
+           DELAY(8NS,-1,15ns))}
+
+     OALSB = {
+        CASE(
+           DATA & TRN_LH, DELAY(6NS,-1,11ns),
+           DATA & TRN_HL, DELAY(6NS,-1,14ns),
+           (EQUAL | GTHAN) & TRN_LH, DELAY(3NS,-1,8ns),
+           (EQUAL | GTHAN) & TRN_HL, DELAY(3NS,-1,9ns),
+           DELAY(7NS,-1,15ns))}
+     OAGRB = {
+        CASE(
+           DATA & TRN_LH, DELAY(6NS,-1,11ns),
+           DATA & TRN_HL, DELAY(6NS,-1,14ns),
+           (EQUAL | LTHAN) & TRN_LH, DELAY(2.5NS,-1,7ns),
+           (EQUAL | LTHAN) & TRN_HL, DELAY(3.5NS,-1,10ns),
+           DELAY(7NS,-1,15ns))}
.ENDS 74F85


.SUBCKT 74HC85 A0 A1 A2 A3 ALSBI AEQBI AGRBI B0 B1 B2 B3 ALSBO AEQBO AGRBO
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(11,3) DPWR DGND
+     A0 A1 A2 A3 ALSBI AEQBI AGRBI B0 B1 B2 B3
+     OALSB_O OAEQB_O OAGRB_O
+     D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     nand3 = {~(A3 & B3)}
+     nand2 = {~(A2 & B2)}
+     nand1 = {~(A1 & B1)}
+     nand0 = {~(A0 & B0)}
+     nor3 = {~((A3 & nand3) | (B3 & nand3))}
+     nor2 = {~((A2 & nand2) | (B2 & nand2))}
+     nor1 = {~((A1 & nand1) | (B1 & nand1))}
+     nor0 = {~((A0 & nand0) | (B0 & nand0))}
+     OAGRB_O = {~((B3 & nand3) | (B2 & nand2 & nor3) | (B1 & nand1 & nor3 & nor2) |
+          (B0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & ALSBI) |
+          (nor3 & nor2 & nor1 & nor0 & AEQBI))}
+     OAEQB_O = {nor3 & nor2 & AEQBI & nor1 & nor0}
+     OALSB_O = {~((A3 & nand3) | (A2 & nand2 & nor3) | (A1 & nand1 & nor3 & nor2) |
+          (A0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & AGRBI) |
+          (nor3 & nor2 & nor1 & nor0 & AEQBI))}
U2DLY PINDLY(3,0,11) DPWR DGND
+     OALSB_O OAEQB_O OAGRB_O
+     A0 A1 A2 A3 ALSBI AEQBI AGRBI B0 B1 B2 B3
+     ALSBO AEQBO AGRBO
+     IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     DATA = {CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) |
+                 CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0)}
+     LTHAN = {CHANGED(ALSBI,0)}
+     GTHAN = {CHANGED(AGRBI,0)}
+     EQUAL = {CHANGED(AEQBI,0)}
+
+  PINDLY:
+     AEQBO = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,-1,40NS),
+           DATA & TRN_HL, DELAY(-1,-1,40NS),
+           EQUAL & TRN_LH, DELAY(-1,-1,29NS),
+           EQUAL & TRN_HL, DELAY(-1,-1,29NS),
+           DELAY(-1,-1,41NS))}
+
+     ALSBO = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,-1,46NS),
+           DATA & TRN_HL, DELAY(-1,-1,46NS),
+           (EQUAL | GTHAN) & TRN_LH, DELAY(-1,-1,35NS),
+           (EQUAL | GTHAN) & TRN_HL, DELAY(-1,-1,35NS),
+           DELAY(-1,-1,47NS))}
+     AGRBO = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,-1,46NS),
+           DATA & TRN_HL, DELAY(-1,-1,46NS),
+           (EQUAL | LTHAN) & TRN_LH, DELAY(-1,-1,35NS),
+           (EQUAL | LTHAN) & TRN_HL, DELAY(-1,-1,35NS),
+           DELAY(-1,-1,47NS))}
.ENDS 74HC85


.SUBCKT 74HC85A A0 A1 A2 A3 ALTBI AEQBI AGTBI B0 B1 B2 B3 ALTBO AEQBO AGTBO
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(11,3) DPWR DGND
+     A0 A1 A2 A3 ALTBI AEQBI AGTBI B0 B1 B2 B3
+     ALTBO_O AEQBO_O AGTBO_O
+     D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     nand3 = {~(A3 & B3)}
+     nand2 = {~(A2 & B2)}
+     nand1 = {~(A1 & B1)}
+     nand0 = {~(A0 & B0)}
+     nor3 = {~((A3 & nand3) | (B3 & nand3))}
+     nor2 = {~((A2 & nand2) | (B2 & nand2))}
+     nor1 = {~((A1 & nand1) | (B1 & nand1))}
+     nor0 = {~((A0 & nand0) | (B0 & nand0))}
+     AGTBO_O = {~((B3 & nand3) | (B2 & nand2 & nor3) | (B1 & nand1 & nor3 & nor2) |
+          (B0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & ALTBI) |
+          (nor3 & nor2 & nor1 & nor0 & AEQBI))}
+     AEQBO_O = {nor3 & nor2 & AEQBI & nor1 & nor0}
+     ALTBO_O = {~((A3 & nand3) | (A2 & nand2 & nor3) | (A1 & nand1 & nor3 & nor2) |
+          (A0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & AGTBI) |
+          (nor3 & nor2 & nor1 & nor0 & AEQBI))}
U2DLY PINDLY(3,0,11) DPWR DGND
+     ALTBO_O AEQBO_O AGTBO_O
+     A0 A1 A2 A3 ALTBI AEQBI AGTBI B0 B1 B2 B3
+     ALTBO AEQBO AGTBO
+     IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     DATA = {CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) |
+                 CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0)}
+     LTHAN = {CHANGED(ALTBI,0)}
+     GTHAN = {CHANGED(AGTBI,0)}
+     EQUAL = {CHANGED(AEQBI,0)}
+
+  PINDLY:
+     AEQBO = {
+        CASE(
+           DATA, DELAY(-1,22ns,40ns),
+           EQUAL, DELAY(-1,17ns,29ns),
+           DELAY(-1,23ns,41ns))}
+
+     ALTBO = {
+        CASE(
+           DATA, DELAY(-1,26ns,46ns),
+           (GTHAN | EQUAL), DELAY(-1,24ns,41ns),
+           DELAY(-1,27ns,47ns))}
+
+     AGTBO = {
+        CASE(
+           DATA, DELAY(-1,26ns,46ns),
+           (LTHAN | EQUAL), DELAY(-1,21ns,41ns),
+           DELAY(-1,27ns,47ns))}
.ENDS 74HC85A


.SUBCKT 74HCT85 A0 A1 A2 A3 IALSB IAEQB IAGRB B0 B1 B2 B3 QALSB QAEQB QAGRB
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(11,3) DPWR DGND
+     A0 A1 A2 A3 IALSB IAEQB IAGRB B0 B1 B2 B3
+     OALSB_O OAEQB_O OAGRB_O
+     D0_GATE IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     nand3 = {~(A3 & B3)}
+     nand2 = {~(A2 & B2)}
+     nand1 = {~(A1 & B1)}
+     nand0 = {~(A0 & B0)}
+     nor3 = {~((A3 & nand3) | (B3 & nand3))}
+     nor2 = {~((A2 & nand2) | (B2 & nand2))}
+     nor1 = {~((A1 & nand1) | (B1 & nand1))}
+     nor0 = {~((A0 & nand0) | (B0 & nand0))}
+     OAGRB_O = {~((B3 & nand3) | (B2 & nand2 & nor3) | (B1 & nand1 & nor3 & nor2) |
+          (B0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & IALSB) |
+          (nor3 & nor2 & nor1 & nor0 & IAEQB))}
+     OAEQB_O = {nor3 & nor2 & IAEQB & nor1 & nor0}
+     OALSB_O = {~((A3 & nand3) | (A2 & nand2 & nor3) | (A1 & nand1 & nor3 & nor2) |
+          (A0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & IAGRB) |
+          (nor3 & nor2 & nor1 & nor0 & IAEQB))}
U2DLY PINDLY(3,0,11) DPWR DGND
+     OALSB_O OAEQB_O OAGRB_O
+     A0 A1 A2 A3 IALSB IAEQB IAGRB B0 B1 B2 B3
+     QALSB QAEQB QAGRB
+     IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     DATA = {CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) |
+                 CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0)}
+     LTHAN = {CHANGED(IALSB,0)}
+     GTHAN = {CHANGED(IAGRB,0)}
+     EQUAL = {CHANGED(IAEQB,0)}
+
+  PINDLY:
+     QAEQB = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,24NS,40NS),
+           DATA & TRN_HL, DELAY(-1,24NS,40NS),
+           EQUAL & TRN_LH, DELAY(-1,18NS,31NS),
+           EQUAL & TRN_HL, DELAY(-1,18NS,31NS),
+           DELAY(-1,25NS,41NS))}
+
+     QALSB = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,26NS,44NS),
+           DATA & TRN_HL, DELAY(-1,26NS,44NS),
+           (EQUAL | GTHAN) & TRN_LH, DELAY(-1,18NS,31NS),
+           (EQUAL | GTHAN) & TRN_HL, DELAY(-1,18NS,31NS),
+           DELAY(-1,27NS,45NS))}
+     QAGRB = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,26NS,44NS),
+           DATA & TRN_HL, DELAY(-1,26NS,44NS),
+           (EQUAL | GTHAN) & TRN_LH, DELAY(-1,18NS,31NS),
+           (EQUAL | GTHAN) & TRN_HL, DELAY(-1,18NS,31NS),
+           DELAY(-1,27NS,45NS))}
.ENDS 74HCT85


.SUBCKT 74LS85 A0 A1 A2 A3 ALTBI AEQBI AGTBI B0 B1 B2 B3 ALTBO AEQBO AGTBO
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(11,3) DPWR DGND
+     A0 A1 A2 A3 ALTBI AEQBI AGTBI B0 B1 B2 B3
+     ALTBO_O AEQBO_O AGTBO_O
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     nand3 = {~(A3 & B3)}
+     nand2 = {~(A2 & B2)}
+     nand1 = {~(A1 & B1)}
+     nand0 = {~(A0 & B0)}
+     nor3 = {~((A3 & nand3) | (B3 & nand3))}
+     nor2 = {~((A2 & nand2) | (B2 & nand2))}
+     nor1 = {~((A1 & nand1) | (B1 & nand1))}
+     nor0 = {~((A0 & nand0) | (B0 & nand0))}
+     AGTBO_O = {~((B3 & nand3) | (B2 & nand2 & nor3) | (B1 & nand1 & nor3 & nor2) |
+          (B0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & ALTBI) |
+          (nor3 & nor2 & nor1 & nor0 & AEQBI))}
+     AEQBO_O = {nor3 & nor2 & AEQBI & nor1 & nor0}
+     ALTBO_O = {~((A3 & nand3) | (A2 & nand2 & nor3) | (A1 & nand1 & nor3 & nor2) |
+          (A0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & AGTBI) |
+          (nor3 & nor2 & nor1 & nor0 & AEQBI))}
U2DLY PINDLY(3,0,11) DPWR DGND
+     ALTBO_O AEQBO_O AGTBO_O
+     A0 A1 A2 A3 ALTBI AEQBI AGTBI B0 B1 B2 B3
+     ALTBO AEQBO AGTBO
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     DATA = {CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) |
+                 CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0)}
+     LTHAN = {CHANGED(ALTBI,0)}
+     GTHAN = {CHANGED(AGTBI,0)}
+     EQUAL = {CHANGED(AEQBI,0)}
+
+  PINDLY:
+     AEQBO = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,27ns,45ns),
+           DATA & TRN_HL, DELAY(-1,23ns,45ns),
+           EQUAL & TRN_LH, DELAY(-1,13ns,20ns),
+           EQUAL & TRN_HL, DELAY(-1,13ns,26ns),
+           DELAY(-1,28ns,46ns))}
+
+     ALTBO AGTBO = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,24ns,36ns),
+           DATA & TRN_HL, DELAY(-1,20ns,30ns),
+           (LTHAN | EQUAL | GTHAN) & TRN_LH, DELAY(-1,14ns,22ns),
+           (LTHAN | EQUAL | GTHAN) & TRN_HL, DELAY(-1,11ns,17ns),
+           DELAY(-1,25ns,37ns))}
.ENDS 74LS85


.SUBCKT 74S85 A0 A1 A2 A3 ALTBI AEQBI AGTBI B0 B1 B2 B3 ALTBO AEQBO AGTBO
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(11,3) DPWR DGND
+     A0 A1 A2 A3 ALTBI AEQBI AGTBI B0 B1 B2 B3
+     ALTBO_O AEQBO_O AGTBO_O
+     D0_GATE IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     nand3 = {~(A3 & B3)}
+     nand2 = {~(A2 & B2)}
+     nand1 = {~(A1 & B1)}
+     nand0 = {~(A0 & B0)}
+     nor3 = {~((A3 & nand3) | (B3 & nand3))}
+     nor2 = {~((A2 & nand2) | (B2 & nand2))}
+     nor1 = {~((A1 & nand1) | (B1 & nand1))}
+     nor0 = {~((A0 & nand0) | (B0 & nand0))}
+     AGTBO_O = {~((B3 & nand3) | (B2 & nand2 & nor3) | (B1 & nand1 & nor3 & nor2) |
+          (B0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & ALTBI) |
+          (nor3 & nor2 & nor1 & nor0 & AEQBI))}
+     AEQBO_O = {nor3 & nor2 & AEQBI & nor1 & nor0}
+     ALTBO_O = {~((A3 & nand3) | (A2 & nand2 & nor3) | (A1 & nand1 & nor3 & nor2) |
+          (A0 & nand0 & nor3 & nor2 & nor1) | (nor3 & nor2 & nor1 & nor0 & AGTBI) |
+          (nor3 & nor2 & nor1 & nor0 & AEQBI))}
U2DLY PINDLY(3,0,11) DPWR DGND
+     ALTBO_O AEQBO_O AGTBO_O
+     A0 A1 A2 A3 ALTBI AEQBI AGTBI B0 B1 B2 B3
+     ALTBO AEQBO AGTBO
+     IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     DATA = {CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) |
+                 CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0)}
+     LTHAN = {CHANGED(ALTBI,0)}
+     GTHAN = {CHANGED(AGTBI,0)}
+     EQUAL = {CHANGED(AEQBI,0)}
+
+  PINDLY:
+     AEQBO = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,12ns,18ns),
+           DATA & TRN_HL, DELAY(-1,11ns,16.5ns),
+           EQUAL & TRN_LH, DELAY(-1,7ns,10.5ns),
+           EQUAL & TRN_HL, DELAY(-1,5ns,7.5ns),
+           DELAY(-1,13ns,19ns))}
+
+     ALTBO AGTBO = {
+        CASE(
+           DATA & TRN_LH, DELAY(-1,10.5ns,16ns),
+           DATA & TRN_HL, DELAY(-1,11ns,16.5ns),
+           (LTHAN | EQUAL | GTHAN) & TRN_LH, DELAY(-1,5ns,7.5ns),
+           (LTHAN | EQUAL | GTHAN) & TRN_HL, DELAY(-1,5.5ns,8.5ns),
+           DELAY(-1,12ns,17.5ns))}
.ENDS 74S85


.SUBCKT 7486 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR DGND
+     1A 1B 1Y_O
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(1,0,2) DPWR DGND
+     1Y_O
+     1A 1B
+     1Y
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     1Y = {
+        CASE(
+           CHANGED(1A,0) & 1B=='1 & TRN_LH, DELAY(-1,18ns,30ns),
+           CHANGED(1B,0) & 1A=='1 & TRN_LH, DELAY(-1,18ns,30ns),
+           CHANGED(1A,0) & 1B=='1 & TRN_HL, DELAY(-1,13ns,22ns),
+           CHANGED(1B,0) & 1A=='1 & TRN_HL, DELAY(-1,13ns,22ns),
+           CHANGED(1A,0) & 1B=='0 & TRN_LH, DELAY(-1,15ns,23ns),
+           CHANGED(1B,0) & 1A=='0 & TRN_LH, DELAY(-1,15ns,23ns),
+           CHANGED(1A,0) & 1B=='0 & TRN_HL, DELAY(-1,11ns,17ns),
+           CHANGED(1B,0) & 1A=='0 & TRN_HL, DELAY(-1,11ns,17ns),
+           DELAY(-1,19ns,31ns))}
.ENDS 7486


.SUBCKT 74AC86 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR DGND
+     1A 1B 1Y
+     DLY_AC86 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AC86 ugate (tplhMN=1.5ns tplhTY=3.8ns tplhMX=6.8ns tphlMN=1.5ns 
+                                tphlTY=3.8ns tphlMX=6.2ns)
.ENDS 74AC86


.SUBCKT 74ACT86 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR DGND
+     1A 1B 1Y
+     DLY_ACT86 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT86 ugate (tplhMN=1.5ns tplhTY=5.1ns tplhMX=8.7ns tphlMN=1.5ns 
+                                tphlTY=5.1ns tphlMX=8ns)
.ENDS 74ACT86


.SUBCKT 74ALS86 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR DGND
+     1A 1B 1Y_O
+     D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(1,0,2) DPWR DGND
+     1Y_O
+     1A 1B
+     1Y
+     IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     1Y = {
+        CASE(
+           TRN_LH, DELAY(3ns,-1,17ns),
+           CHANGED(1A,0) & 1B=='0 & TRN_HL, DELAY(2ns,-1,12ns),
+           CHANGED(1B,0) & 1A=='0 & TRN_HL, DELAY(2ns,-1,12ns),
+           CHANGED(1A,0) & 1B=='1 & TRN_HL, DELAY(2ns,-1,10ns),
+           CHANGED(1B,0) & 1A=='1 & TRN_HL, DELAY(2ns,-1,10ns),
+           DELAY(4ns,-1,18ns))}
.ENDS 74ALS86


.SUBCKT 74AS86 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR DGND
+     1A 1B 1Y
+     DLY_AS86 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS86 ugate (tplhTY=3.6ns tphlTY=3.5ns)
.ENDS 74AS86


.SUBCKT 74F86 A0 B0 O0
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR DGND
+     A0 B0 O0_O
+     D0_GATE IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(1,0,2) DPWR DGND
+     O0_O
+     A0 B0
+     O0
+     IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     O0 = {
+        CASE(
+           CHANGED(A0,0) & B0=='1 & TRN_LH, DELAY(3.5ns,5.3ns,7ns),
+           CHANGED(B0,0) & A0=='1 & TRN_LH, DELAY(3.5ns,5.3ns,7ns),
+           CHANGED(A0,0) & B0=='1 & TRN_HL, DELAY(3ns,4.7ns,6.5ns),
+           CHANGED(B0,0) & A0=='1 & TRN_HL, DELAY(3ns,4.7ns,6.5ns),
+           CHANGED(A0,0) & B0=='0 & TRN_LH, DELAY(3ns,4ns,5.5ns),
+           CHANGED(B0,0) & A0=='0 & TRN_LH, DELAY(3ns,4ns,5.5ns),
+           CHANGED(A0,0) & B0=='0 & TRN_HL, DELAY(3ns,4.2ns,5.5ns),
+           CHANGED(B0,0) & A0=='0 & TRN_HL, DELAY(3ns,4.2ns,5.5ns),
+           DELAY(4.5ns,6.3ns,8ns))}
.ENDS 74F86


.SUBCKT 74HC86 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR DGND
+     1A 1B 1Y
+     DLY_HC86 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC86 ugate (tplhTY=12ns tplhMX=20ns tphlTY=12ns tphlMX=20ns)
.ENDS 74HC86


.SUBCKT 74HCT86 1A 1B 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 XOR DPWR DGND
+ 1A 1B 1Y
+ DLY_HCT86 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT86 UGATE(TPLHTY=17NS TPLHMX=32NS TPHLTY=17NS TPHLMX=32NS)
.ENDS 74HCT86


.SUBCKT 74LS86 A1 B1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 XOR DPWR DGND
+ A1 B1 Y1O
+ D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(1,0,2) DPWR DGND
+ Y1O
+ A1 B1
+ Y1
+ IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ PINDLY:
+   Y1 = {
+     CASE(
+           CHANGED(A1,0) & B1=='1 & TRN_LH, DELAY(-1,-1,15NS),
+           CHANGED(B1,0) & A1=='1 & TRN_LH, DELAY(-1,-1,15NS),
+           CHANGED(A1,0) & B1=='1 & TRN_HL, DELAY(-1,-1,15NS),
+           CHANGED(B1,0) & A1=='1 & TRN_HL, DELAY(-1,-1,15NS),
+           CHANGED(A1,0) & B1=='0 & TRN_LH, DELAY(-1,-1,23NS),
+           CHANGED(B1,0) & A1=='0 & TRN_LH, DELAY(-1,-1,23NS),
+           CHANGED(A1,0) & B1=='0 & TRN_HL, DELAY(-1,-1,21NS),
+           CHANGED(B1,0) & A1=='0 & TRN_HL, DELAY(-1,-1,21NS),
+           DELAY(-1,-1,24NS))}
.ENDS 74LS86


.SUBCKT 74LS86A 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR DGND
+     1A 1B 1Y_O
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(1,0,2) DPWR DGND
+     1Y_O
+     1A 1B
+     1Y
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     1Y = {
+        CASE(
+           CHANGED(1A,0) & 1B=='1 & TRN_LH, DELAY(-1,20ns,30ns),
+           CHANGED(1B,0) & 1A=='1 & TRN_LH, DELAY(-1,20ns,30ns),
+           CHANGED(1A,0) & 1B=='1 & TRN_HL, DELAY(-1,13ns,22ns),
+           CHANGED(1B,0) & 1A=='1 & TRN_HL, DELAY(-1,13ns,22ns),
+           CHANGED(1A,0) & 1B=='0 & TRN_LH, DELAY(-1,12ns,23ns),
+           CHANGED(1B,0) & 1A=='0 & TRN_LH, DELAY(-1,12ns,23ns),
+           CHANGED(1A,0) & 1B=='0 & TRN_HL, DELAY(-1,10ns,17ns),
+           CHANGED(1B,0) & 1A=='0 & TRN_HL, DELAY(-1,10ns,17ns),
+           DELAY(-1,19ns,31ns))}
.ENDS 74LS86A


.SUBCKT 74S86 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR DGND
+     1A 1B 1Y
+     DLY_S86 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S86 ugate(tplhTY=7ns tplhMX=10.5ns tphlTY=6.5ns tphlMX=10ns)
.ENDS 74S86


.SUBCKT 74H87 A1 A2 A3 A4 B C Y1 Y2 Y3 Y4
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(6,4) DPWR DGND
+     A1 A2 A3 A4 B C
+     Y1_O Y2_O Y3_O Y4_O
+     D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     bbar = {~B}
+     Y1_O = {(~(A1 & bbar)) ^ C}
+     Y2_O = {(~(A2 & bbar)) ^ C}
+     Y3_O = {(~(A3 & bbar)) ^ C}
+     Y4_O = {(~(A4 & bbar)) ^ C}
U2DLY PINDLY(4,0,6) DPWR DGND
+     Y1_O Y2_O Y3_O Y4_O
+     A1 A2 A3 A4 B C
+     Y1 Y2 Y3 Y4
+     IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     DATA = {CHANGED(A1,0) | CHANGED(A2,0) | CHANGED(A3,0) | CHANGED(A4,0)}
+     CONTROL = {CHANGED(B,0) | CHANGED(C,0)}
+
+  PINDLY:
+     Y1 Y2 Y3 Y4 = {
+        CASE(
+           CONTROL, DELAY(-1,17ns,25ns),
+           DATA & TRN_LH, DELAY(-1,14ns,20ns),
+           DATA & TRN_HL, DELAY(-1,13ns,19ns),
+           DELAY(-1,18ns,26ns))}
.ENDS 74H87


.SUBCKT 7490A R01 R02 R91 R92 CKA CKB QA QB QC QD
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     NAND9 NAND0 CKA $D_HI $D_HI QA_O $D_NC
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     $D_HI NANDC CKB QDBAR $D_HI QB_O $D_NC
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     $D_HI NANDC QB_O $D_HI $D_HI QC_O $D_NC
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     NAND9 NAND0 CKB ANDQ QD_O QD_O QDBAR
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5LOG LOGICEXP(6,4) DPWR DGND
+     R01 R02 R91 R92 QB_O QC_O
+     NAND9 NAND0 NANDC ANDQ
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     NAND0 = {~(R01 & R02)}
+     NAND9 = {~(R91 & R92)}
+     NANDC = {NAND0 & NAND9}
+     ANDQ = {QB_O & QC_O}
U6DLY PINDLY(4,0,4) DPWR DGND
+     QA_O QB_O QC_O QD_O
+     CKA CKB NAND9 NAND0
+     QA QB QC QD
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     CHA = {CHANGED_HL(CKA,0)}
+     CHB = {CHANGED_HL(CKB,0)}
+     SETTO9 = {CHANGED_HL(NAND9,0)}
+     SETTO0 = {CHANGED_HL(NAND0,0)}
+     SET = {SETTO0 | SETTO9}
+
+  PINDLY:
+     QA = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         SETTO9 & TRN_LH, DELAY(-1,20ns,30ns),
+         CHA & TRN_LH, DELAY(-1,10ns,16ns),
+         CHA & TRN_HL, DELAY(-1,12ns,18ns),
+         DELAY(-1,27ns,41ns))}
+
+     QB = {
+       CASE(
+         SET & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,10ns,16ns),
+         CHB & TRN_HL, DELAY(-1,14ns,21ns),
+         DELAY(-1,27ns,41ns))}
+
+     QC = {
+       CASE(
+         SET & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,21ns,32ns),
+         CHB & TRN_HL, DELAY(-1,23ns,35ns),
+         DELAY(-1,27ns,41ns))}
+
+     QD = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         SETTO9 & TRN_LH, DELAY(-1,20ns,30ns),
+         CHB & TRN_LH, DELAY(-1,21ns,32ns),
+         CHB & TRN_HL, DELAY(-1,23ns,35ns),
+         CHA & TRN_LH, DELAY(-1,32ns,48ns),
+         CHA & TRN_HL, DELAY(-1,34ns,50ns),
+         DELAY(-1,35ns,51ns))}
U7CON CONSTRAINT(8) DPWR DGND
+     R01 R02 R91 R92 CKA CKB NAND9 NAND0
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CKA
+     MAXFREQ=32MEG
+
+  FREQ:
+     NODE=CKB
+     MAXFREQ=16MEG
+
+  WIDTH:
+     NODE=CKA
+     MIN_HI=15ns
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=CKB
+     MIN_HI=30ns
+     MIN_LO=30ns
+
+  WIDTH:
+     NODE=R01
+     MIN_HI=15ns
+     WHEN = {NAND9!='0}
+
+  WIDTH:
+     NODE=R02
+     MIN_HI=15ns
+     WHEN = {NAND9!='0}
+
+  WIDTH:
+     NODE=R91
+     MIN_HI=15ns
+     WHEN = {NAND0!='0}
+
+  WIDTH:
+     NODE=R92
+     MIN_HI=15ns
+     WHEN = {NAND0!='0}
+
+  SETUP_HOLD:
+  CLOCK HL = CKA
+  DATA(1) = NAND9
+  SETUPTIME_HI = 25ns
+  MESSAGE = "SETUP ERROR - R91 R92 SETUP < 25ns"
+
+  SETUP_HOLD:
+  CLOCK HL = CKB
+  DATA(1) = NAND9
+  SETUPTIME_HI = 25ns
+  MESSAGE = "SETUP ERROR - R91 R92 SETUP < 25ns"
+
+  SETUP_HOLD:
+  CLOCK HL = CKA
+  DATA(1) = NAND0
+  SETUPTIME_HI = 25ns
+  WHEN = {NAND9!='0}
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
+
+  SETUP_HOLD:
+  CLOCK HL = CKB
+  DATA(1) = NAND0
+  SETUPTIME_HI = 25ns
+  WHEN = {NAND9!='0}
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
.ENDS 7490A


.SUBCKT 74LS90 R01 R02 R91 R92 CKA CKB QA QB QC QD
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     NAND9 NAND0 CKA $D_HI $D_HI QA_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     $D_HI NANDC CKB QDBAR $D_HI QB_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     $D_HI NANDC QB_O $D_HI $D_HI QC_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     NAND9 NAND0 CKB ANDQ QD_O QD_O QDBAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5LOG LOGICEXP(6,4) DPWR DGND
+     R01 R02 R91 R92 QB_O QC_O
+     NAND9 NAND0 NANDC ANDQ
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     NAND0 = {~(R01 & R02)}
+     NAND9 = {~(R91 & R92)}
+     NANDC = {NAND0 & NAND9}
+     ANDQ = {QB_O & QC_O}
U6DLY PINDLY(4,0,4) DPWR DGND
+     QA_O QB_O QC_O QD_O
+     CKA CKB NAND9 NAND0
+     QA QB QC QD
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     CHA = {CHANGED_HL(CKA,0)}
+     CHB = {CHANGED_HL(CKB,0)}
+     SETTO9 = {CHANGED_HL(NAND9,0)}
+     SETTO0 = {CHANGED_HL(NAND0,0)}
+     SET = {SETTO0 | SETTO9}
+
+  PINDLY:
+     QA = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         SETTO9 & TRN_LH, DELAY(-1,20ns,30ns),
+         CHA & TRN_LH, DELAY(-1,10ns,16ns),
+         CHA & TRN_HL, DELAY(-1,12ns,18ns),
+         DELAY(-1,27ns,41ns))}
+
+     QB = {
+       CASE(
+         SET & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,10ns,16ns),
+         CHB & TRN_HL, DELAY(-1,14ns,21ns),
+         DELAY(-1,27ns,41ns))}
+
+     QC = {
+       CASE(
+         SET & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,21ns,32ns),
+         CHB & TRN_HL, DELAY(-1,23ns,35ns),
+         DELAY(-1,27ns,41ns))}
+
+     QD = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         SETTO9 & TRN_LH, DELAY(-1,20ns,30ns),
+         CHB & TRN_LH, DELAY(-1,21ns,32ns),
+         CHB & TRN_HL, DELAY(-1,23ns,35ns),
+         CHA & TRN_LH, DELAY(-1,32ns,48ns),
+         CHA & TRN_HL, DELAY(-1,34ns,50ns),
+         DELAY(-1,35ns,51ns))}
U7CON CONSTRAINT(8) DPWR DGND
+     R01 R02 R91 R92 CKA CKB NAND9 NAND0
+     IO_LS IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CKA
+     MAXFREQ=32MEG
+
+  FREQ:
+     NODE=CKB
+     MAXFREQ=16MEG
+
+  WIDTH:
+     NODE=CKA
+     MIN_HI=15ns
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=CKB
+     MIN_HI=30ns
+     MIN_LO=30ns
+
+  WIDTH:
+     NODE=R01
+     MIN_HI=30ns
+     WHEN = {NAND9!='0}
+
+  WIDTH:
+     NODE=R02
+     MIN_HI=30ns
+     WHEN = {NAND9!='0}
+
+  WIDTH:
+     NODE=R91
+     MIN_HI=30ns
+     WHEN = {NAND0!='0}
+
+  WIDTH:
+     NODE=R92
+     MIN_HI=30ns
+     WHEN = {NAND0!='0}
+
+  SETUP_HOLD:
+  CLOCK HL = CKA
+  DATA(1) = NAND9
+  SETUPTIME_HI = 25ns
+  MESSAGE = "SETUP ERROR - R91 R92 SETUP < 25ns"
+
+  SETUP_HOLD:
+  CLOCK HL = CKB
+  DATA(1) = NAND9
+  SETUPTIME_HI = 25ns
+  MESSAGE = "SETUP ERROR - R91 R92 SETUP < 25ns"
+
+  SETUP_HOLD:
+  CLOCK HL = CKA
+  DATA(1) = NAND0
+  SETUPTIME_HI = 25ns
+  WHEN = {NAND9!='0}
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
+
+  SETUP_HOLD:
+  CLOCK HL = CKB
+  DATA(1) = NAND0
+  SETUPTIME_HI = 25ns
+  WHEN = {NAND9!='0}
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
.ENDS 74LS90


.SUBCKT 7491A A B CLK QH QHBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     A B RIN
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 inva(2) DPWR DGND
+     CLK RIN CLKBAR SIN
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(8) DPWR DGND
+     $D_HI $D_HI CLKBAR SIN S1 S2 S3 S4 S5 S6 S7 RIN R1 R2 R3
+     R4 R5 R6 R7 S1 S2 S3 S4 S5 S6 S7 QH_O R1 R2 R3 R4 R5 R6
+     R7 QHBAR_O
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4DLY PINDLY(2,0,0) DPWR DGND
+     QH_O QHBAR_O
+     QH QHBAR
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+     PINDLY:
+       QH QHBAR = {
+         CASE(
+          TRN_LH, DELAY(-1,24ns,40ns),
+          TRN_HL, DELAY(-1,27ns,40ns),
+          DELAY(-1,28ns,41ns))}
U5CON CONSTRAINT(3) DPWR DGND
+     A B CLK
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=25ns
+     MIN_LO=25ns
+
+  SETUP_HOLD:
+     CLOCK LH=CLK
+     DATA(2)=A B
+     SETUPTIME=25ns
.ENDS 7491A


.SUBCKT 74LS91 A B CLK QH QHBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     A B RIN
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 inva(2) DPWR DGND
+     CLK RIN CLKBAR SIN
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(8) DPWR DGND
+     $D_HI $D_HI CLKBAR SIN S1 S2 S3 S4 S5 S6 S7 RIN R1 R2 R3
+     R4 R5 R6 R7 S1 S2 S3 S4 S5 S6 S7 QH_O R1 R2 R3 R4 R5 R6
+     R7 QHBAR_O
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4DLY PINDLY(2,0,0) DPWR DGND
+     QH_O QHBAR_O
+     QH QHBAR
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+     PINDLY:
+       QH QHBAR = {
+         CASE(
+          TRN_LH, DELAY(-1,24ns,40ns),
+          TRN_HL, DELAY(-1,27ns,40ns),
+          DELAY(-1,28ns,41ns))}
U5CON CONSTRAINT(3) DPWR DGND
+     A B CLK
+     IO_LS IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=25ns
+     MIN_LO=25ns
+
+  SETUP_HOLD:
+     CLOCK LH=CLK
+     DATA(2)=A B
+     SETUPTIME=25ns
.ENDS 74LS91


.SUBCKT 7492A R01 R02 CKA CKB QA QB QC QD
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     $D_HI NAND0 CKA $D_HI $D_HI QA_O $D_NC
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     $D_HI NAND0 CKB QCBAR $D_HI QB_O $D_NC
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     $D_HI NAND0 CKB QB_O $D_HI QC_O QCBAR
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     $D_HI NAND0 QC_O $D_HI $D_HI QD_O $D_NC
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5 nand(2) DPWR DGND
+     R01 R02 NAND0
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6DLY PINDLY(4,0,3) DPWR DGND
+     QA_O QB_O QC_O QD_O
+     CKA CKB NAND0
+     QA QB QC QD
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     CHA = {CHANGED_HL(CKA,0)}
+     CHB = {CHANGED_HL(CKB,0)}
+     SETTO0 = {CHANGED_HL(NAND0,0)}
+
+  PINDLY:
+     QA = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHA & TRN_LH, DELAY(-1,10ns,16ns),
+         CHA & TRN_HL, DELAY(-1,12ns,18ns),
+         DELAY(-1,27ns,41ns))}
+
+     QB = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,10ns,16ns),
+         CHB & TRN_HL, DELAY(-1,14ns,21ns),
+         DELAY(-1,27ns,41ns))}
+
+     QC = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,10ns,16ns),
+         CHB & TRN_HL, DELAY(-1,14ns,21ns),
+         DELAY(-1,27ns,41ns))}
+
+     QD = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,21ns,32ns),
+         CHB & TRN_HL, DELAY(-1,23ns,35ns),
+         CHA & TRN_LH, DELAY(-1,32ns,48ns),
+         CHA & TRN_HL, DELAY(-1,34ns,50ns),
+         DELAY(-1,35ns,51ns))}
U7CON CONSTRAINT(5) DPWR DGND
+     R01 R02 CKA CKB NAND0
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CKA
+     MAXFREQ=32MEG
+
+  FREQ:
+     NODE=CKB
+     MAXFREQ=16MEG
+
+  WIDTH:
+     NODE=CKA
+     MIN_HI=15ns
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=CKB
+     MIN_HI=30ns
+     MIN_LO=30ns
+
+  WIDTH:
+     NODE=R01
+     MIN_HI=15ns
+
+  WIDTH:
+     NODE=R02
+     MIN_HI=15ns
+
+  SETUP_HOLD:
+  CLOCK HL = CKA
+  DATA(1) = NAND0
+  SETUPTIME_HI = 25ns
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
+
+  SETUP_HOLD:
+  CLOCK HL = CKB
+  DATA(1) = NAND0
+  SETUPTIME_HI = 25ns
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
.ENDS 7492A


.SUBCKT 74LS92 R01 R02 CKA CKB QA QB QC QD
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     $D_HI NAND0 CKA $D_HI $D_HI QA_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     $D_HI NAND0 CKB QCBAR $D_HI QB_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     $D_HI NAND0 CKB QB_O $D_HI QC_O QCBAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     $D_HI NAND0 QC_O $D_HI $D_HI QD_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5 nand(2) DPWR DGND
+     R01 R02 NAND0
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6DLY PINDLY(4,0,3) DPWR DGND
+     QA_O QB_O QC_O QD_O
+     CKA CKB NAND0
+     QA QB QC QD
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     CHA = {CHANGED_HL(CKA,0)}
+     CHB = {CHANGED_HL(CKB,0)}
+     SETTO0 = {CHANGED_HL(NAND0,0)}
+
+  PINDLY:
+     QA = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHA & TRN_LH, DELAY(-1,10ns,16ns),
+         CHA & TRN_HL, DELAY(-1,12ns,18ns),
+         DELAY(-1,27ns,41ns))}
+
+     QB = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,10ns,16ns),
+         CHB & TRN_HL, DELAY(-1,14ns,21ns),
+         DELAY(-1,27ns,41ns))}
+
+     QC = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,10ns,16ns),
+         CHB & TRN_HL, DELAY(-1,14ns,21ns),
+         DELAY(-1,27ns,41ns))}
+
+     QD = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,21ns,32ns),
+         CHB & TRN_HL, DELAY(-1,23ns,35ns),
+         CHA & TRN_LH, DELAY(-1,32ns,48ns),
+         CHA & TRN_HL, DELAY(-1,34ns,50ns),
+         DELAY(-1,35ns,51ns))}
U7CON CONSTRAINT(5) DPWR DGND
+     R01 R02 CKA CKB NAND0
+     IO_LS IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CKA
+     MAXFREQ=32MEG
+
+  FREQ:
+     NODE=CKB
+     MAXFREQ=16MEG
+
+  WIDTH:
+     NODE=CKA
+     MIN_HI=15ns
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=CKB
+     MIN_HI=30ns
+     MIN_LO=30ns
+
+  WIDTH:
+     NODE=R01
+     MIN_HI=30ns
+
+  WIDTH:
+     NODE=R02
+     MIN_HI=30ns
+
+  SETUP_HOLD:
+  CLOCK HL = CKA
+  DATA(1) = NAND0
+  SETUPTIME_HI = 25ns
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
+
+  SETUP_HOLD:
+  CLOCK HL = CKB
+  DATA(1) = NAND0
+  SETUPTIME_HI = 25ns
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
.ENDS 74LS92


.SUBCKT 7493A R01 R02 CKA CKB QA QB QC QD
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     $D_HI NAND0 CKA $D_HI $D_HI QA_O $D_NC
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     $D_HI NAND0 CKB $D_HI $D_HI QB_O $D_NC
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     $D_HI NAND0 QB_O $D_HI $D_HI QC_O $D_NC
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     $D_HI NAND0 QC_O $D_HI $D_HI QD_O $D_NC
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5 nand(2) DPWR DGND
+     R01 R02 NAND0
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6DLY PINDLY(4,0,3) DPWR DGND
+     QA_O QB_O QC_O QD_O
+     CKA CKB NAND0
+     QA QB QC QD
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     CHA = {CHANGED_HL(CKA,0)}
+     CHB = {CHANGED_HL(CKB,0)}
+     SETTO0 = {CHANGED_HL(NAND0,0)}
+
+  PINDLY:
+     QA = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHA & TRN_LH, DELAY(-1,10ns,16ns),
+         CHA & TRN_HL, DELAY(-1,12ns,18ns),
+         DELAY(-1,27ns,41ns))}
+
+     QB = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,10ns,16ns),
+         CHB & TRN_HL, DELAY(-1,14ns,21ns),
+         DELAY(-1,27ns,41ns))}
+
+     QC = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,21ns,32ns),
+         CHB & TRN_HL, DELAY(-1,23ns,35ns),
+         DELAY(-1,27ns,41ns))}
+
+     QD = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,34ns,51ns),
+         CHB & TRN_HL, DELAY(-1,34ns,51ns),
+         CHA & TRN_LH, DELAY(-1,46ns,70ns),
+         CHA & TRN_HL, DELAY(-1,46ns,70ns),
+         DELAY(-1,47ns,71ns))}
U7CON CONSTRAINT(5) DPWR DGND
+     R01 R02 CKA CKB NAND0
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CKA
+     MAXFREQ=32MEG
+
+  FREQ:
+     NODE=CKB
+     MAXFREQ=16MEG
+
+  WIDTH:
+     NODE=CKA
+     MIN_HI=15ns
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=CKB
+     MIN_HI=30ns
+     MIN_LO=30ns
+
+  WIDTH:
+     NODE=R01
+     MIN_HI=15ns
+
+  WIDTH:
+     NODE=R02
+     MIN_HI=15ns
+
+  SETUP_HOLD:
+  CLOCK HL = CKA
+  DATA(1) = NAND0
+  SETUPTIME_HI = 25ns
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
+
+  SETUP_HOLD:
+  CLOCK HL = CKB
+  DATA(1) = NAND0
+  SETUPTIME_HI = 25ns
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
.ENDS 7493A


.SUBCKT 74HC93 MR1 MR2 CP0BAR CP1BAR Q0 Q1 Q2 Q3
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     $D_HI NAND0 CP0BAR $D_HI $D_HI Q0_O $D_NC
+     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     $D_HI NAND0 CP1BAR $D_HI $D_HI Q1_O $D_NC
+     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     $D_HI NAND0 Q1_O $D_HI $D_HI Q2_O $D_NC
+     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     $D_HI NAND0 Q2_O $D_HI $D_HI Q3_O $D_NC
+     D0_EFF IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5 nand(2) DPWR DGND
+     MR1 MR2 NAND0
+     D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6DLY PINDLY(4,0,3) DPWR DGND
+     Q0_O Q1_O Q2_O Q3_O
+     CP0BAR CP1BAR NAND0
+     Q0 Q1 Q2 Q3
+     IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     CHA = {CHANGED_HL(CP0BAR,0)}
+     CHB = {CHANGED_HL(CP1BAR,0)}
+     SETTO0 = {CHANGED_HL(NAND0,0)}
+
+  PINDLY:
+     Q0 = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,18ns,31ns),
+         CHA, DELAY(-1,15ns,25ns),
+         DELAY(-1,19ns,32ns))}
+
+     Q1 = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,18ns,31ns),
+         CHB, DELAY(-1,16ns,27ns),
+         DELAY(-1,19ns,32ns))}
+
+     Q2 = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,18ns,31ns),
+         CHB, DELAY(-1,22ns,37ns),
+         DELAY(-1,23ns,38ns))}
+
+     Q3 = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,18ns,31ns),
+         CHB, DELAY(-1,29ns,49ns),
+         DELAY(-1,30ns,50ns))}
U7CON CONSTRAINT(5) DPWR DGND
+     MR1 MR2 CP0BAR CP1BAR NAND0
+     IO_HC IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CP0BAR
+     MAXFREQ=24MEG
+
+  FREQ:
+     NODE=CP1BAR
+     MAXFREQ=24MEG
+
+  WIDTH:
+     NODE=CP0BAR
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=CP1BAR
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=MR1
+     MIN_HI=20ns
+
+  WIDTH:
+     NODE=MR2
+     MIN_HI=20ns
+
+  SETUP_HOLD:
+  CLOCK HL = CP0BAR
+  DATA(1) = NAND0
+  SETUPTIME_HI = 13ns
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 13ns"
+
+  SETUP_HOLD:
+  CLOCK HL = CP1BAR
+  DATA(1) = NAND0
+  SETUPTIME_HI = 13ns
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 13ns"
.ENDS 74HC93


.SUBCKT 74HCT93 MR1 MR2 CP0BAR CP1BAR Q0 Q1 Q2 Q3
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     $D_HI NAND0 CP0BAR $D_HI $D_HI Q0_O $D_NC
+     D0_EFF IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     $D_HI NAND0 CP1BAR $D_HI $D_HI Q1_O $D_NC
+     D0_EFF IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     $D_HI NAND0 Q1_O $D_HI $D_HI Q2_O $D_NC
+     D0_EFF IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     $D_HI NAND0 Q2_O $D_HI $D_HI Q3_O $D_NC
+     D0_EFF IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5 nand(2) DPWR DGND
+     MR1 MR2 NAND0
+     D0_GATE IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6DLY PINDLY(4,0,3) DPWR DGND
+     Q0_O Q1_O Q2_O Q3_O
+     CP0BAR CP1BAR NAND0
+     Q0 Q1 Q2 Q3
+     IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     CHA = {CHANGED_HL(CP0BAR,0)}
+     CHB = {CHANGED_HL(CP1BAR,0)}
+     SETTO0 = {CHANGED_HL(NAND0,0)}
+
+  PINDLY:
+     Q0 = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,17ns,33ns),
+         CHA, DELAY(-1,18ns,34ns),
+         DELAY(-1,19ns,35ns))}
+
+     Q1 = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,17ns,33ns),
+         CHB, DELAY(-1,18ns,34ns),
+         DELAY(-1,19ns,35ns))}
+
+     Q2 = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,17ns,33ns),
+         CHB, DELAY(-1,24ns,46ns),
+         DELAY(-1,25ns,47ns))}
+
+     Q3 = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,17ns,33ns),
+         CHB, DELAY(-1,30ns,58ns),
+         DELAY(-1,31ns,59ns))}
U7CON CONSTRAINT(5) DPWR DGND
+     MR1 MR2 CP0BAR CP1BAR NAND0
+     IO_HCT IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CP0BAR
+     MAXFREQ=24MEG
+
+  FREQ:
+     NODE=CP1BAR
+     MAXFREQ=24MEG
+
+  WIDTH:
+     NODE=CP0BAR
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=CP1BAR
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=MR1
+     MIN_HI=20ns
+
+  WIDTH:
+     NODE=MR2
+     MIN_HI=20ns
+
+  SETUP_HOLD:
+  CLOCK HL = CP0BAR
+  DATA(1) = NAND0
+  SETUPTIME_HI = 13ns
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 13ns"
+
+  SETUP_HOLD:
+  CLOCK HL = CP1BAR
+  DATA(1) = NAND0
+  SETUPTIME_HI = 13ns
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 13ns"
.ENDS 74HCT93


.SUBCKT 74LS93 R01 R02 CKA CKB QA QB QC QD
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     $D_HI NAND0 CKA $D_HI $D_HI QA_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     $D_HI NAND0 CKB $D_HI $D_HI QB_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     $D_HI NAND0 QB_O $D_HI $D_HI QC_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     $D_HI NAND0 QC_O $D_HI $D_HI QD_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5 nand(2) DPWR DGND
+     R01 R02 NAND0
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6DLY PINDLY(4,0,3) DPWR DGND
+     QA_O QB_O QC_O QD_O
+     CKA CKB NAND0
+     QA QB QC QD
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     CHA = {CHANGED_HL(CKA,0)}
+     CHB = {CHANGED_HL(CKB,0)}
+     SETTO0 = {CHANGED_HL(NAND0,0)}
+
+  PINDLY:
+     QA = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHA & TRN_LH, DELAY(-1,10ns,16ns),
+         CHA & TRN_HL, DELAY(-1,12ns,18ns),
+         DELAY(-1,27ns,41ns))}
+
+     QB = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,10ns,16ns),
+         CHB & TRN_HL, DELAY(-1,14ns,21ns),
+         DELAY(-1,27ns,41ns))}
+
+     QC = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,21ns,32ns),
+         CHB & TRN_HL, DELAY(-1,23ns,35ns),
+         DELAY(-1,27ns,41ns))}
+
+     QD = {
+       CASE(
+         SETTO0 & TRN_HL, DELAY(-1,26ns,40ns),
+         CHB & TRN_LH, DELAY(-1,34ns,51ns),
+         CHB & TRN_HL, DELAY(-1,34ns,51ns),
+         CHA & TRN_LH, DELAY(-1,46ns,70ns),
+         CHA & TRN_HL, DELAY(-1,46ns,70ns),
+         DELAY(-1,47ns,71ns))}
U7CON CONSTRAINT(5) DPWR DGND
+     R01 R02 CKA CKB NAND0
+     IO_LS IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CKA
+     MAXFREQ=32MEG
+
+  FREQ:
+     NODE=CKB
+     MAXFREQ=16MEG
+
+  WIDTH:
+     NODE=CKA
+     MIN_HI=15ns
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=CKB
+     MIN_HI=30ns
+     MIN_LO=30ns
+
+  WIDTH:
+     NODE=R01
+     MIN_HI=30ns
+
+  WIDTH:
+     NODE=R02
+     MIN_HI=30ns
+
+  SETUP_HOLD:
+  CLOCK HL = CKA
+  DATA(1) = NAND0
+  SETUPTIME_HI = 25ns
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
+
+  SETUP_HOLD:
+  CLOCK HL = CKB
+  DATA(1) = NAND0
+  SETUPTIME_HI = 25ns
+  MESSAGE = "SETUP ERROR - R01 R02 SETUP < 25ns"
.ENDS 74LS93


.SUBCKT 7494 PE1 PE2 CLR CLK SER P1A P1B P1C P1D P2A P2B P2C P2D QD
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     PA CLRBAR CLKBAR SER SERBAR QA QABAR
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     PB CLRBAR CLKBAR QA QABAR QB QBBAR
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     PC CLRBAR CLKBAR QB QBBAR QC QCBAR
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     PD CLRBAR CLKBAR QC QCBAR QD_O $D_NC
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5LOG LOGICEXP(13,7) DPWR DGND
+     PE1 PE2 CLR CLK SER P1A P1B P1C P1D P2A P2B P2C P2D
+     CLRBAR CLKBAR SERBAR PA PB PC PD
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     CLRBAR = {~CLR}
+     CLKBAR = {~CLK}
+     SERBAR = {~SER}
+
+     PA = {~((P1A & PE1) | (P2A & PE2))}
+     PB = {~((P1B & PE1) | (P2B & PE2))}
+     PC = {~((P1C & PE1) | (P2C & PE2))}
+     PD = {~((P1D & PE1) | (P2D & PE2))}
U6DLY PINDLY(1,0,3) DPWR DGND
+     QD_O
+     CLK CLR PD
+     QD
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     QD = {
+        CASE(
+           CHANGED_HL(PD,0) & TRN_LH, DELAY(-1,-1,35ns),
+           CHANGED_LH(CLR,0) & TRN_HL, DELAY(-1,-1,40ns),
+           CHANGED_LH(CLK,0), DELAY(-1,25ns,40ns),
+           DELAY(-1,26ns,41ns))}
U7CON CONSTRAINT(7) DPWR DGND
+     SER CLK CLR PA PB PC PD
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=35ns
+     MIN_LO=35ns
+
+  WIDTH:
+     NODE=CLR
+     MIN_HI=30ns
+
+  WIDTH:
+     NODE=PA
+     MIN_LO=30ns
+     MESSAGE="(PRESET ENABLE & PA INPUT) PULSE WIDTH IS LESS THAN 30ns"
+
+  WIDTH:
+     NODE=PB
+     MIN_LO=30ns
+     MESSAGE="(PRESET ENABLE & PB INPUT) PULSE WIDTH IS LESS THAN 30ns"
+
+  WIDTH:
+     NODE=PC
+     MIN_LO=30ns
+     MESSAGE="(PRESET ENABLE & PC INPUT) PULSE WIDTH IS LESS THAN 30ns"
+
+  WIDTH:
+     NODE=PD
+     MIN_LO=30ns
+     MESSAGE="(PRESET ENABLE & PD INPUT) PULSE WIDTH IS LESS THAN 30ns"
+
+  SETUP_HOLD:
+     CLOCK LH=CLK
+     DATA(1)=SER
+     SETUPTIME_LO=25ns
+     SETUPTIME_HI=35ns
+     WHEN={CLR!='1 | PA!='0}
.ENDS 7494


.SUBCKT 7495 SERIN A B C D MODE QA QB QC QD CLK1 CLK2
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(11,5) DPWR DGND
+ A B C D MODE SERIN CLK1 CLK2 QAO QBO QCO
+ CLOCK DA DB DC DD
+ D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+   CLOCK = {(~CLK1 & ~MODE) | (~CLK2 & MODE)}
+   DA = {(A & MODE) | (SERIN & ~MODE)}
+   DB = {(B & MODE) | (QAO & ~MODE)}
+   DC = {(C & MODE) | (QBO & ~MODE)}
+   DD = {(D & MODE) | (QCO & ~MODE)}
U2 DFF(4) DPWR DGND
+ $D_HI $D_HI CLOCK
+ DA DB DC DD
+ QAO QBO QCO QDO
+ $D_NC $D_NC $D_NC $D_NC
+ D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 PINDLY(4,0,0) DPWR DGND
+ QAO QBO QCO QDO QA QB QC QD
+ IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ PINDLY:
+   QA QB QC QD = {
+   CASE(
+     TRN_LH, DELAY(-1,-1,35NS),
+     TRN_HL, DELAY(-1,-1,35NS),
+     DELAY(-1,-1,36NS))}
U4 CONSTRAINT(7) DPWR DGND
+ CLK1 CLK2 A B C D SERIN
+ IO_STD IO_LEVEL={IO_LEVEL}
+ FREQ:
+  NODE = CLK1
+  MAXFREQ = 25MEG
+ FREQ:
+  NODE = CLK2
+  MAXFREQ = 25MEG
+ WIDTH:
+  NODE = CLK1
+  MIN_HI = 15NS
+  MIN_LO = 15NS
+ WIDTH:
+  NODE = CLK2
+  MIN_HI = 15NS
+  MIN_LO = 15NS
+ SETUP_HOLD:
+  CLOCK HL = CLK1
+  DATA(5) = A B C D SERIN
+  SETUPTIME = 10NS
+ SETUP_HOLD:
+  CLOCK HL = CLK2
+  DATA(5) = A B C D SERIN
+  SETUPTIME = 10NS
.ENDS 7495


.SUBCKT 7495A MODE CLK1 CLK2 SER A B C D QA QB QC QD
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(4) DPWR DGND
+     $D_HI $D_HI CLKLR JA JB JC JD KA KB KC KD
+     QA_O QB_O QC_O QD_O $D_NC $D_NC $D_NC $D_NC
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2LOG LOGICEXP(12,9) DPWR DGND
+     MODE SER CLK1 CLK2 A B C D QA_O QB_O QC_O QD_O
+     CLKLR JA JB JC JD KA KB KC KD
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     modebar = {~MODE}
+     CLKLR = {(CLK1 & modebar) | (CLK2 & MODE)}
+     JA = {((SER & modebar) | (A & MODE))}
+     JB = {((QA_O & modebar) | (B & MODE))}
+     JC = {((QB_O & modebar) | (C & MODE))}
+     JD = {((QC_O & modebar) | (D & MODE))}
+     KA = {~JA}
+     KB = {~JB}
+     KC = {~JC}
+     KD = {~JD}
U3DLY PINDLY(4,0,0) DPWR DGND
+     QA_O QB_O QC_O QD_O
+     QA QB QC QD
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     QA QB QC QD = {
+        CASE(
+           TRN_LH, DELAY(-1,18ns,27ns),
+           TRN_HL, DELAY(-1,21ns,32ns),
+           DELAY(-1,22ns,33ns))}
U4CON CONSTRAINT(8) DPWR DGND
+     CLK1 CLK2 SER A B C D MODE
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CLK1
+     MAXFREQ=25MEG
+
+  FREQ:
+     NODE=CLK2
+     MAXFREQ=25MEG
+
+  WIDTH:
+     NODE=CLK1
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=CLK2
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  SETUP_HOLD:
+     DATA(1)=SER
+     CLOCK HL=CLK1
+     SETUPTIME=15ns
+     WHEN = {MODE!='1}
+
+  SETUP_HOLD:
+     DATA(4)=A B C D
+     CLOCK HL=CLK2
+     SETUPTIME=15ns
+     WHEN = {MODE!='0}
+
+  SETUP_HOLD:
+     DATA(1)=MODE
+     CLOCK HL=CLK1
+     SETUPTIME_LO=15ns
+     MESSAGE="CLOCK ENABLE > 15ns"
+
+  SETUP_HOLD:
+     DATA(1)=MODE
+     CLOCK LH=CLK1
+     SETUPTIME_HI=5ns
+     MESSAGE="CLOCK INHIBIT > 5ns"
+
+  SETUP_HOLD:
+     DATA(1)=MODE
+     CLOCK HL=CLK2
+     SETUPTIME_HI=15ns
+     MESSAGE="CLOCK ENABLE > 15ns"
+
+  SETUP_HOLD:
+     DATA(1)=MODE
+     CLOCK LH=CLK2
+     SETUPTIME_LO=5ns
+     MESSAGE="CLOCK INHIBIT > 5ns"
.ENDS 7495A


.SUBCKT 74AS95 MODE CLK1 CLK2 SER A B C D QA QB QC QD
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(4) DPWR DGND
+     $D_HI $D_HI CLKLR JA JB JC JD KA KB KC KD
+     QA_O QB_O QC_O QD_O $D_NC $D_NC $D_NC $D_NC
+     D0_EFF IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2LOG LOGICEXP(12,9) DPWR DGND
+     MODE SER CLK1 CLK2 A B C D QA_O QB_O QC_O QD_O
+     CLKLR JA JB JC JD KA KB KC KD
+     D0_GATE IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     modebar = {~MODE}
+     CLKLR = {(CLK1 & modebar) | (CLK2 & MODE)}
+     JA = {((SER & modebar) | (A & MODE))}
+     JB = {((QA_O & modebar) | (B & MODE))}
+     JC = {((QB_O & modebar) | (C & MODE))}
+     JD = {((QC_O & modebar) | (D & MODE))}
+     KA = {~JA}
+     KB = {~JB}
+     KC = {~JC}
+     KD = {~JD}
U3DLY PINDLY(4,0,0) DPWR DGND
+     QA_O QB_O QC_O QD_O
+     QA QB QC QD
+     IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     QA QB QC QD = {
+        CASE(
+           TRN_LH, DELAY(2ns,-1,10ns),
+           TRN_HL, DELAY(2ns,-1,9.5ns),
+           DELAY(3ns,-1,11ns))}
U4CON CONSTRAINT(8) DPWR DGND
+     CLK1 CLK2 SER A B C D MODE
+     IO_AS00 IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CLK1
+     MAXFREQ=100MEG
+
+  FREQ:
+     NODE=CLK2
+     MAXFREQ=100MEG
+
+  WIDTH:
+     NODE=CLK1
+     MIN_HI=5ns
+     MIN_LO=5ns
+
+  WIDTH:
+     NODE=CLK2
+     MIN_HI=5ns
+     MIN_LO=5ns
+
+  SETUP_HOLD:
+     DATA(1)=SER
+     CLOCK HL=CLK1
+     SETUPTIME=2ns
+     HOLDTIME=2.5ns
+     WHEN = {MODE!='1}
+
+  SETUP_HOLD:
+     DATA(4)=A B C D
+     CLOCK HL=CLK2
+     SETUPTIME=2ns
+     HOLDTIME=2.5ns
+     WHEN = {MODE!='0}
+
+  SETUP_HOLD:
+     DATA(1)=MODE
+     CLOCK HL=CLK1
+     SETUPTIME_LO=12ns
+     MESSAGE="CLOCK ENABLE > 12ns"
+
+  SETUP_HOLD:
+     DATA(1)=MODE
+     CLOCK LH=CLK1
+     SETUPTIME_HI=2.5ns
+     MESSAGE="CLOCK INHIBIT > 2.5ns"
+
+  SETUP_HOLD:
+     DATA(1)=MODE
+     CLOCK HL=CLK2
+     SETUPTIME_HI=12ns
+     MESSAGE="CLOCK ENABLE > 12ns"
+
+  SETUP_HOLD:
+     DATA(1)=MODE
+     CLOCK HL=CLK1
+     HOLDTIME=3ns
.ENDS 74AS95


.SUBCKT 74LS95B MODE CLK1 CLK2 SER A B C D QA QB QC QD
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(4) DPWR DGND
+     $D_HI $D_HI CLKLR JA JB JC JD KA KB KC KD
+     QA_O QB_O QC_O QD_O $D_NC $D_NC $D_NC $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2LOG LOGICEXP(12,9) DPWR DGND
+     MODE SER CLK1 CLK2 A B C D QA_O QB_O QC_O QD_O
+     CLKLR JA JB JC JD KA KB KC KD
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     modebar = {~MODE}
+     CLKLR = {(CLK1 & modebar) | (CLK2 & MODE)}
+     JA = {((SER & modebar) | (A & MODE))}
+     JB = {((QA_O & modebar) | (B & MODE))}
+     JC = {((QB_O & modebar) | (C & MODE))}
+     JD = {((QC_O & modebar) | (D & MODE))}
+     KA = {~JA}
+     KB = {~JB}
+     KC = {~JC}
+     KD = {~JD}
U3DLY PINDLY(4,0,0) DPWR DGND
+     QA_O QB_O QC_O QD_O
+     QA QB QC QD
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     QA QB QC QD = {
+        CASE(
+           TRN_LH, DELAY(-1,18ns,27ns),
+           TRN_HL, DELAY(-1,21ns,32ns),
+           DELAY(-1,22ns,33ns))}
U4CON CONSTRAINT(8) DPWR DGND
+     CLK1 CLK2 SER A B C D MODE
+     IO_LS IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CLK1
+     MAXFREQ=25MEG
+
+  FREQ:
+     NODE=CLK2
+     MAXFREQ=25MEG
+
+  WIDTH:
+     NODE=CLK1
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=CLK2
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  SETUP_HOLD:
+     DATA(1)=SER
+     CLOCK HL=CLK1
+     SETUPTIME=20ns
+     HOLDTIME=10ns
+     WHEN = {MODE!='1}
+
+  SETUP_HOLD:
+     DATA(4)=A B C D
+     CLOCK HL=CLK2
+     SETUPTIME=20ns
+     HOLDTIME=10ns
+     WHEN = {MODE!='0}
+
+  SETUP_HOLD:
+     DATA(1)=MODE
+     CLOCK HL=CLK1
+     SETUPTIME_LO=20ns
+     MESSAGE="CLOCK ENABLE > 20ns"
+
+  SETUP_HOLD:
+     DATA(1)=MODE
+     CLOCK LH=CLK1
+     SETUPTIME_HI=20ns
+     MESSAGE="CLOCK INHIBIT > 20ns"
+
+  SETUP_HOLD:
+     DATA(1)=MODE
+     CLOCK HL=CLK2
+     SETUPTIME_HI=20ns
+     MESSAGE="CLOCK ENABLE > 20ns"
+
+  SETUP_HOLD:
+     DATA(1)=MODE
+     CLOCK LH=CLK2
+     SETUPTIME_LO=20ns
+     MESSAGE="CLOCK INHIBIT > 20ns"
.ENDS 74LS95B


.SUBCKT 7496 CLRBAR CLK PE SER A B C D E QA QB QC QD QE
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     PA CLRBAR CLKBAR SER SERBAR QA_O QABAR
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     PB CLRBAR CLKBAR QA_O QABAR QB_O QBBAR
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     PC CLRBAR CLKBAR QB_O QBBAR QC_O QCBAR
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     PD CLRBAR CLKBAR QC_O QCBAR QD_O QDBAR
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5 JKFF(1) DPWR DGND
+     PE1 CLRBAR CLKBAR QD_O QDBAR QE_O $D_NC
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6LOG LOGICEXP(8,7) DPWR DGND
+     CLK SER PE A B C D E
+     CLKBAR SERBAR PA PB PC PD PE1
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     CLKBAR = {~CLK}
+     SERBAR = {~SER}
+     PA = {~(PE & A)}
+     PB = {~(PE & B)}
+     PC = {~(PE & C)}
+     PD = {~(PE & D)}
+     PE1 = {~(PE & E)}
U7DLY PINDLY(5,0,7) DPWR DGND
+     QA_O QB_O QC_O QD_O QE_O
+     CLRBAR CLK PA PB PC PD PE1
+     QA QB QC QD QE
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     PRE = {CHANGED_HL(PA,0) | CHANGED_HL(PB,0) | CHANGED_HL(PC,0) |
+           CHANGED_HL(PD,0) | CHANGED_HL(PE1,0)}
+
+  PINDLY:
+     QA QB QC QD QE = {
+       CASE(
+          PRE & TRN_LH, DELAY(-1,28ns,35ns),
+          CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(-1,-1,55ns),
+          CHANGED_LH(CLK,0), DELAY(-1,25ns,40ns),
+          DELAY(-1,29ns,56ns))}
U8CON CONSTRAINT(8) DPWR DGND
+     CLK CLRBAR SER PA PB PC PD PE1
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=35ns
+     MIN_LO=35ns
+
+  WIDTH:
+     NODE=CLRBAR
+     MIN_LO=30ns
+
+  WIDTH:
+     NODE=PA
+     MIN_LO=30ns
+     MESSAGE = "(PE & A) PULSE < 30ns"
+
+  WIDTH:
+     NODE=PB
+     MIN_LO=30ns
+     MESSAGE = "(PE & B) PULSE < 30ns"
+
+  WIDTH:
+     NODE=PC
+     MIN_LO=30ns
+     MESSAGE = "(PE & C) PULSE < 30ns"
+
+  WIDTH:
+     NODE=PD
+     MIN_LO=30ns
+     MESSAGE = "(PE & D) PULSE < 30ns"
+
+  WIDTH:
+     NODE=PE1
+     MIN_LO=30ns
+     MESSAGE = "(PE & E) PULSE < 30ns"
+
+  SETUP_HOLD:
+     CLOCK LH=CLK
+     DATA(1) = SER
+     SETUPTIME=30ns
+     WHEN={CLRBAR!='0 | PA!='0}
.ENDS 7496


.SUBCKT 74LS96 CLRBAR CLK PE SER A B C D E QA QB QC QD QE
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     PA CLRBAR CLKBAR SER SERBAR QA_O QABAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     PB CLRBAR CLKBAR QA_O QABAR QB_O QBBAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     PC CLRBAR CLKBAR QB_O QBBAR QC_O QCBAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     PD CLRBAR CLKBAR QC_O QCBAR QD_O QDBAR
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5 JKFF(1) DPWR DGND
+     PE1 CLRBAR CLKBAR QD_O QDBAR QE_O $D_NC
+     D0_EFF IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6LOG LOGICEXP(8,7) DPWR DGND
+     CLK SER PE A B C D E
+     CLKBAR SERBAR PA PB PC PD PE1
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     CLKBAR = {~CLK}
+     SERBAR = {~SER}
+     PA = {~(PE & A)}
+     PB = {~(PE & B)}
+     PC = {~(PE & C)}
+     PD = {~(PE & D)}
+     PE1 = {~(PE & E)}
U7DLY PINDLY(5,0,7) DPWR DGND
+     QA_O QB_O QC_O QD_O QE_O
+     CLRBAR CLK PA PB PC PD PE1
+     QA QB QC QD QE
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     PRE = {CHANGED_HL(PA,0) | CHANGED_HL(PB,0) | CHANGED_HL(PC,0) |
+           CHANGED_HL(PD,0) | CHANGED_HL(PE1,0)}
+
+  PINDLY:
+     QA QB QC QD QE = {
+       CASE(
+          PRE & TRN_LH, DELAY(-1,28ns,35ns),
+          CHANGED_HL(CLRBAR,0) & TRN_HL, DELAY(-1,-1,55ns),
+          CHANGED_LH(CLK,0), DELAY(-1,25ns,40ns),
+          DELAY(-1,29ns,56ns))}
U8CON CONSTRAINT(8) DPWR DGND
+     CLK CLRBAR SER PA PB PC PD PE1
+     IO_LS IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CLK
+     MAXFREQ=25MEG
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=CLRBAR
+     MIN_LO=30ns
+
+  WIDTH:
+     NODE=PA
+     MIN_LO=30ns
+     MESSAGE = "(PE & A) PULSE < 30ns"
+
+  WIDTH:
+     NODE=PB
+     MIN_LO=30ns
+     MESSAGE = "(PE & B) PULSE < 30ns"
+
+  WIDTH:
+     NODE=PC
+     MIN_LO=30ns
+     MESSAGE = "(PE & C) PULSE < 30ns"
+
+  WIDTH:
+     NODE=PD
+     MIN_LO=30ns
+     MESSAGE = "(PE & D) PULSE < 30ns"
+
+  WIDTH:
+     NODE=PE1
+     MIN_LO=30ns
+     MESSAGE = "(PE & E) PULSE < 30ns"
+
+  SETUP_HOLD:
+     CLOCK LH=CLK
+     DATA(1) = SER
+     SETUPTIME=30ns
+     WHEN={CLRBAR!='0 | PA!='0}
.ENDS 74LS96


.SUBCKT 7497 CLK STROBE ENI UNI/CAS CLR B0 B1 B2 B3 B4 B5 Z Y ENO
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(6) DPWR DGND
+     $D_HI CLRBAR CLKBAR ENIBAR J2 J3 J4 J5 J6 ENIBAR J2 J3 J4 J5 J6
+     QA QB QC QD QE QF QABAR QBBAR QCBAR QDBAR QEBAR QFBAR
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2LOG LOGICEXP(23,11) DPWR DGND
+     CLK STROBE ENI UNI/CAS CLR B0 B1 B2 B3 B4 B5 QA QB QC QD QE QF
+     QABAR QBBAR QCBAR QDBAR QEBAR QFBAR
+     CLKBAR CLRBAR ENIBAR J2 J3 J4 J5 J6 Z_O Y_O ENO_O
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     CLKBAR = {~CLK}
+     CLRBAR = {~CLR}
+     ENIBAR = {~ENI}
+     rateclk = {~(CLK | STROBE)}
+     J2 = {QA & ENIBAR}
+     J3 = {QA & QB & ENIBAR}
+     J4 = {QA & QB & QC & ENIBAR}
+     J5 = {QA & QB & QC & QD & ENIBAR}
+     J6 = {QA & QB & QC & QD & QE & ENIBAR}
+     ENO_O = {~(QA & QB & QC & QD & QE & QF & ENIBAR)}
+     rate5 = {B5 & rateclk & QABAR}
+     rate4 = {B4 & rateclk & QA & QBBAR}
+     rate3 = {B3 & rateclk & QA & QB & QCBAR}
+     rate2 = {B2 & rateclk & QA & QB & QC & QDBAR}
+     rate1 = {B1 & rateclk & QA & QB & QC & QD & QEBAR}
+     rate0 = {B0 & rateclk & QA & QB & QC & QD & QE & QFBAR}
+     Z_O = {~(rate5 | rate4 | rate3 | rate2 | rate1 | rate0)}
+     Y_O = {~(UNI/CAS & Z_O)}
U3DLY PINDLY(3,0,11) DPWR DGND
+     ENO_O Z_O Y_O
+     ENI STROBE CLK CLR UNI/CAS B0 B1 B2 B3 B4 B5
+     ENO Z Y
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     RATE = {CHANGED(B0,0) | CHANGED(B1,0) | CHANGED(B2,0) | CHANGED(B3,0) |
+                CHANGED(B4,0) | CHANGED(B5,0)}
+     CLOCK = {CHANGED(CLK,0)}
+     CLEAR = {CHANGED_LH(CLR,0)}
+     UNI = {CHANGED(UNI/CAS,0)}
+     STR = {CHANGED(STROBE,0)}
+     ENABLE = {CHANGED(ENI,0)}
+
+  PINDLY:
+     ENO = {
+       CASE(
+          CLOCK & TRN_LH, DELAY(-1,19ns,30ns),
+          CLOCK & TRN_HL, DELAY(-1,22ns,33ns),
+          ENABLE & TRN_LH, DELAY(-1,13ns,20ns),
+          ENABLE & TRN_HL, DELAY(-1,14ns,21ns),
+          DELAY(-1,23ns,34ns))}
+
+     Z = {
+       CASE(
+          CLOCK & TRN_LH, DELAY(-1,12ns,18ns),
+          CLOCK & TRN_HL, DELAY(-1,17ns,26ns),
+          STR & TRN_LH, DELAY(-1,12ns,18ns),
+          STR & TRN_HL, DELAY(-1,15ns,23ns),
+          CLEAR & TRN_HL, DELAY(-1,15ns,23ns),
+          RATE & TRN_LH, DELAY(-1,6ns,10ns),
+          RATE & TRN_HL, DELAY(-1,9ns,14ns),
+          DELAY(-1,18ns,27ns))}
+
+     Y = {
+        CASE(
+           CLOCK & TRN_LH, DELAY(-1,26ns,39ns),
+           CLOCK & TRN_HL, DELAY(-1,20ns,30ns),
+           CLEAR & TRN_LH, DELAY(-1,24ns,36ns),
+           STR & TRN_LH, DELAY(-1,19ns,30ns),
+           STR & TRN_HL, DELAY(-1,22ns,33ns),
+           RATE, DELAY(-1,15ns,23ns),
+           UNI & TRN_LH, DELAY(-1,9ns,14ns),
+           UNI & TRN_HL, DELAY(-1,6ns,10ns),
+           DELAY(-1,27ns,40ns))}
U4CON CONSTRAINT(3) DPWR DGND
+     CLK CLR ENI
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  FREQ:
+     NODE=CLK
+     MAXFREQ=25MEG
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=CLR
+     MIN_HI=15ns
+
+  SETUP_HOLD:
+     CLOCK LH=CLK
+     DATA(1)=ENI
+     SETUPTIME=25ns
+     WHEN={CLR!='1}
+
+  SETUP_HOLD:
+     CLOCK HL=CLK
+     DATA(1)=ENI
+     HOLDTIME=20ns
+     WHEN={CLR!='1}
.ENDS 7497


.SUBCKT 74100 1D1 1D2 1D3 1D4 1C 1Q1 1Q2 1Q3 1Q4
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 DLTCH(4) DPWR DGND
+     $D_HI $D_HI 1C 1D1 1D2 1D3 1D4
+     1Q1 1Q2 1Q3 1Q4 $D_NC $D_NC $D_NC $D_NC
+     DLY_100 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_100 ugff (tpgqlhTY=16ns tpgqlhMX=30ns tpgqhlTY=7ns
+                          tpgqhlMX=15ns tpdqlhTY=16ns tpdqlhMX=30ns
+                          tpdqhlTY=14ns tpdqhlMX=25ns twghMN=20ns
+                          tsudgMN=20ns thdgMN=5ns)
.ENDS 74100


.SUBCKT 74H101 PREBAR CLK J1A J1B J2A J2B K1A K1B K2A K2B Q QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     PREBAR $D_HI CLK J K Q_O QBAR_O
+     D0_EFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2LOG LOGICEXP(9,2) DPWR DGND
+     J1A J1B J2A J2B K1A K1B K2A K2B CLK
+     J K
+     D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     J = {((J1A & J1B) | (J2A & J2B)) & CLK}
+     K = {((K1A & K1B) | (K2A & K2B)) & CLK}
U3DLY PINDLY(2,0,2) DPWR DGND
+     Q_O QBAR_O
+     PREBAR CLK
+     Q QBAR
+     IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     PRE = {CHANGED_HL(PREBAR,0)}
+     CLOCK = {CHANGED_HL(CLK,0)}
+
+  PINDLY:
+     Q QBAR = {
+        CASE(
+           PRE & TRN_HL & CLK=='1, DELAY(-1,15ns,20ns),
+           PRE & TRN_HL & CLK=='0, DELAY(-1,23ns,35ns),
+           PRE & TRN_LH, DELAY(-1,8ns,12ns),
+           CLOCK & TRN_LH, DELAY(-1,10ns,15ns),
+           CLOCK & TRN_HL, DELAY(-1,16ns,20ns),
+           DELAY(-1,24ns,36ns))}
U4CON CONSTRAINT(4) DPWR DGND
+     PREBAR CLK J K
+     IO_H IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=10ns
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=PREBAR
+     MIN_LO=16ns
+
+  SETUP_HOLD:
+     CLOCK HL=CLK
+     DATA(2)= J K 
+     SETUPTIME_HI=10ns
+     SETUPTIME_LO=13ns
.ENDS 74H101


.SUBCKT 74H102 PREBAR CLRBAR CLK J1 J2 J3 K1 K2 K3 Q QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     PREBAR CLRBAR CLK J K Q_O QBAR_O
+     D0_EFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2LOG LOGICEXP(7,2) DPWR DGND
+     J1 J2 J3 K1 K2 K3 CLK
+     J K
+     D0_GATE IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     J = {(J1 & J2 & J3) & CLK}
+     K = {(K1 & K2 & K3) & CLK}
U3DLY PINDLY(2,0,3) DPWR DGND
+     Q_O QBAR_O
+     PREBAR CLRBAR CLK
+     Q QBAR
+     IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     PRE = {CHANGED_HL(PREBAR,0)}
+     CLR = {CHANGED_HL(CLRBAR,0)}
+     CLOCK = {CHANGED_HL(CLK,0)}
+
+  PINDLY:
+     Q QBAR = {
+       CASE(
+          (PRE | CLR) & TRN_LH, DELAY(-1,8ns,12ns),
+          (PRE | CLR) & TRN_HL & CLK=='1, DELAY(-1,15ns,20ns),
+          (PRE | CLR) & TRN_HL & CLK=='0, DELAY(-1,23ns,35ns),
+          CLOCK & TRN_LH, DELAY(-1,10ns,15ns),
+          CLOCK & TRN_HL, DELAY(-1,16ns,20ns),
+          DELAY(-1,24ns,36ns))}
U4CON CONSTRAINT(5) DPWR DGND
+     PREBAR CLRBAR CLK J K
+     IO_H IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=10ns
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=PREBAR
+     MIN_LO=16ns
+
+  WIDTH:
+     NODE=CLRBAR
+     MIN_LO=16ns
+
+  SETUP_HOLD:
+     CLOCK HL=CLK
+     DATA(2)= J K
+     SETUPTIME_HI=10ns
+     SETUPTIME_LO=13ns
.ENDS 74H102


.SUBCKT 74H103 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     $D_HI 1CLRBAR 1CLK 1J 1K 1Q_O 1QBAR_O
+     D0_EFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(2,0,2) DPWR DGND
+     1Q_O 1QBAR_O
+     1CLRBAR 1CLK
+     1Q 1QBAR
+     IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     CLR = {CHANGED_HL(1CLRBAR,0)}
+     CLOCK = {CHANGED_HL(1CLK,0)}
+
+  PINDLY:
+     1Q 1QBAR = {
+       CASE(
+           CLR & TRN_LH, DELAY(-1,8ns,12ns),
+           CLR & TRN_HL & 1CLK=='1, DELAY(-1,15ns,20ns),
+           CLR & TRN_HL & 1CLK=='0, DELAY(-1,23ns,35ns),
+           CLOCK & TRN_LH, DELAY(-1,10ns,15ns),
+           CLOCK & TRN_HL, DELAY(-1,16ns,20ns),
+           DELAY(-1,24ns,36ns))}
U3CON CONSTRAINT(4) DPWR DGND
+     1CLRBAR 1CLK 1J 1K
+     IO_H IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=1CLK
+     MIN_HI=10ns
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=1CLRBAR
+     MIN_LO=16ns
+
+  SETUP_HOLD:
+     CLOCK HL=1CLK
+     DATA(2)= 1J 1K
+     SETUPTIME_HI=10ns
+     SETUPTIME_LO=13ns
.ENDS 74H103


.SUBCKT 74104 PREBAR CLRBAR CLK JK J1 J2 J3 K1 K2 K3 Q QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     PREBAR CLRBAR CLK J K SJ SK
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     PREBAR CLRBAR CLKBAR SJ SK Q_O QBAR_O
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3LOG LOGICEXP(8,3) DPWR DGND
+     JK J1 J2 J3 K1 K2 K3 CLK
+     J K CLKBAR
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     J = {JK & J1 & J2 & J3}
+     K = {JK & K1 & K2 & K3}
+     CLKBAR = {~CLK}
U4DLY PINDLY(2,0,1) DPWR DGND
+     Q_O QBAR_O
+     CLK
+     Q QBAR
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     Q QBAR = {
+       CASE(
+          TRN_LH, DELAY(-1,9ns,15ns),
+          TRN_HL, DELAY(-1,16ns,25ns),
+          DELAY(-1,17ns,26ns))}
 
U5CON CONSTRAINT(5) DPWR DGND
+     PREBAR CLRBAR CLK J K
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=PREBAR
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=CLRBAR
+     MIN_LO=20ns
+
+  SETUP_HOLD:
+     CLOCK LH=CLK
+     DATA(2) = J K
+     SETUPTIME_LO=10ns
+     SETUPTIME_HI=35ns
.ENDS 74104


.SUBCKT 74105 PREBAR CLRBAR CLK JK J1 J2BAR J3 K1 K2BAR K3 Q QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     PREBAR CLRBAR CLK J K SJ SK
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     PREBAR CLRBAR CLKBAR SJ SK Q_O QBAR_O
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3LOG LOGICEXP(8,3) DPWR DGND
+     JK J1 J2BAR J3 K1 K2BAR K3 CLK
+     J K CLKBAR
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     j2 = {~J2BAR}
+     k2 = {~K2BAR}
+     J = {JK & J1 & j2 & J3}
+     K = {JK & K1 & k2 & K3}
+     CLKBAR = {~CLK}
U4DLY PINDLY(2,0,1) DPWR DGND
+     Q_O QBAR_O
+     CLK
+     Q QBAR
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     Q QBAR = {
+       CASE(
+          TRN_LH, DELAY(-1,9ns,15ns),
+          TRN_HL, DELAY(-1,16ns,25ns),
+          DELAY(-1,17ns,26ns))}
 
U5CON CONSTRAINT(5) DPWR DGND
+     PREBAR CLRBAR CLK J K
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=PREBAR
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=CLRBAR
+     MIN_LO=20ns
+
+  SETUP_HOLD:
+     CLOCK LH=CLK
+     DATA(2) = J K
+     SETUPTIME_LO=10ns
+     SETUPTIME_HI=35ns
.ENDS 74105


.SUBCKT 74H106 1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1J 1K 1Q_O 1QBAR_O
+     D0_EFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(2,0,3) DPWR DGND
+     1Q_O 1QBAR_O
+     1PREBAR 1CLRBAR 1CLK
+     1Q 1QBAR
+     IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     PRE = {CHANGED_HL(1PREBAR,0)}
+     CLR = {CHANGED_HL(1CLRBAR,0)}
+     CLOCK = {CHANGED_HL(1CLK,0)}
+
+  PINDLY:
+     1Q 1QBAR = {
+       CASE(
+          (PRE | CLR) & TRN_LH, DELAY(-1,8ns,12ns),
+          (PRE | CLR) & TRN_HL & 1CLK=='1, DELAY(-1,15ns,20ns),
+          (PRE | CLR) & TRN_HL & 1CLK=='0, DELAY(-1,23ns,35ns),
+          CLOCK & TRN_LH, DELAY(-1,10ns,15ns),
+          CLOCK & TRN_HL, DELAY(-1,16ns,20ns),
+          DELAY(-1,24ns,36ns))}
U4CON CONSTRAINT(5) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1J 1K
+     IO_H IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=1CLK
+     MIN_HI=10ns
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=1PREBAR
+     MIN_LO=16ns
+
+  WIDTH:
+     NODE=1CLRBAR
+     MIN_LO=16ns
+
+  SETUP_HOLD:
+     CLOCK HL=1CLK
+     DATA(2)= 1J 1K
+     SETUPTIME_HI=10ns
+     SETUPTIME_LO=13ns
.ENDS 74H106


.SUBCKT 74107 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 SRFF(1) DPWR DGND
+     $D_HI 1CLRBAR 1CLK MJ MK SJ SK
+     D0_GFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 SRFF(1) DPWR DGND
+     $D_HI 1CLRBAR CLKBAR SJ SK 1Q_O 1QBAR_O
+     D0_GFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3LOG LOGICEXP(5,3) DPWR DGND
+     1CLK 1J 1K 1Q_O 1QBAR_O
+     MJ MK CLKBAR
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   LOGIC:
+     CLKBAR={~1CLK}
+     jbar={~1J}
+     kbar={~1K}
+     MJ={(1J & 1K & 1QBAR_O) | (1J & kbar)}
+     MK={(1J & 1K & 1Q_O) | (jbar & 1K)}
U4DLY PINDLY(2,0,0) DPWR DGND
+     1Q_O 1QBAR_O
+     1Q 1QBAR
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+   PINDLY:
+     1Q 1QBAR={
+        CASE(
+           TRN_LH, DELAY(-1,16ns,25ns),
+           TRN_HL, DELAY(-1,25ns,40ns),
+           DELAY(-1,26ns,41ns))}
U5CON CONSTRAINT(2) DPWR DGND
+     1CLK 1CLRBAR
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=1CLK
+     MIN_HI=20ns
+     MIN_LO=47ns
+
+  WIDTH:
+     NODE=1CLRBAR
+     MIN_LO=25ns
.ENDS 74107


.SUBCKT 74HC107 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     $D_HI 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     DLY_HC107 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC107 ueff(tppcqlhTY=25ns tppcqlhMX=31ns tppcqhlTY=25ns
+                   tppcqhlMX=31ns twpclMN=25ns tpclkqlhTY=20ns
+                   tpclkqlhMX=25ns tpclkqhlTY=20ns tpclkqhlMX=25ns
+                   twclklMN=20ns twclkhMN=20ns tsudclkMN=25ns
+                   tsupcclkhMN=25ns)
.ENDS 74HC107


.SUBCKT 74HCT107
+ 1J 1K 1CPBAR 1RBAR 1Q 1QBAR
+ OPTIONAL:  DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS:  MNTYMXDLY=0 IO_LEVEL=0
UBUF BUF DPWR DGND
+ 1CPBAR 1CPBARST
+ D0_GATE IO_HCT_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U1 JKFF(1) DPWR DGND
+ $D_HI 1RBAR 1CPBARST
+ 1J 1K 1QO 1QBARO
+ D0_EFF IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(2,0,2) DPWR DGND
+ 1QO 1QBARO
+ 1CPBAR 1RBAR
+ 1Q 1QBAR
+ IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+          EDGE = {CHANGED_HL(1CPBAR,0)}
+          RESET = {CHANGED_HL(1RBAR,0)}
+ PINDLY:
+          1Q 1QBAR = {
+            CASE(
+              RESET & (TRN_LH | TRN_HL), DELAY(-1,19NS,31NS),
+              EDGE & TRN_LH, DELAY(-1,19NS,32NS),
+              EDGE & TRN_HL, DELAY(-1,19NS,32NS),
+              DELAY(-1,20NS,33NS))}
U3 CONSTRAINT(4) DPWR DGND
+ 1CPBAR 1J 1K 1RBAR
+ IO_HCT IO_LEVEL={IO_LEVEL}
+ SETUP_HOLD:
+             CLOCK HL = 1CPBAR
+             DATA(2) = 1J 1K
+             SETUPTIME = 8NS
+ SETUP_HOLD:
+             CLOCK HL = 1CPBAR
+             DATA(1) = 1RBAR
+             SETUPTIME_HI = 7NS
+ WIDTH:
+             NODE = 1CPBAR
+             MIN_LO = 8NS
+             MIN_HI = 8NS
+ WIDTH:
+             NODE = 1RBAR
+             MIN_LO = 8NS
+ FREQ:
+             NODE = 1CPBAR
+             MAXFREQ = 70MEG
.ENDS 74HCT107


.SUBCKT 74LS107A 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     $D_HI 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     DLY_LS107 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS107 ueff(tppcqlhTY=15ns tppcqlhMX=20ns tppcqhlTY=15ns
+                   tppcqhlMX=20ns twpclMN=25ns tpclkqlhTY=15ns
+                   tpclkqlhMX=20ns tpclkqhlTY=15ns tpclkqhlMX=20ns
+                   twclkhMN=20ns tsudclkMN=20ns
+                   tsupcclkhMN=25ns)
.ENDS 74LS107A


.SUBCKT 74H108 CLK CLRBAR 1PREBAR 1J 1K 2PREBAR 2J 2K 1Q 1QBAR 2Q 2QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR CLRBAR CLK 1J 1K 1Q_O 1QBAR_O
+     D0_EFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     2PREBAR CLRBAR CLK 2J 2K 2Q_O 2QBAR_O
+     D0_EFF IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3DLY PINDLY(4,0,4) DPWR DGND
+     1Q_O 1QBAR_O 2Q_O 2QBAR_O
+     1PREBAR 2PREBAR CLRBAR CLK
+     1Q 1QBAR 2Q 2QBAR
+     IO_H MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     PCL1 = {CHANGED_HL(CLRBAR,0) | CHANGED_HL(1PREBAR,0)}
+     PCL2 = {CHANGED_HL(CLRBAR,0) | CHANGED_HL(2PREBAR,0)}
+     CLOCK = {CHANGED_HL(CLK,0)}
+
+  PINDLY:
+     1Q 1QBAR = {
+       CASE(
+          PCL1 & TRN_HL & CLK=='1, DELAY(-1,15ns,20ns),
+          PCL1 & TRN_HL & CLK=='0, DELAY(-1,23ns,35ns),
+          PCL1 & TRN_LH, DELAY(-1,8ns,12ns),
+          CLOCK & TRN_LH, DELAY(-1,10ns,15ns),
+          CLOCK & TRN_HL, DELAY(-1,16ns,20ns),
+          DELAY(-1,24ns,36ns))}
+
+     2Q 2QBAR = {
+       CASE(
+          PCL2 & TRN_HL & CLK=='1, DELAY(-1,15ns,20ns),
+          PCL2 & TRN_HL & CLK=='0, DELAY(-1,23ns,35ns),
+          PCL2 & TRN_LH, DELAY(-1,8ns,12ns),
+          CLOCK & TRN_LH, DELAY(-1,10ns,15ns),
+          CLOCK & TRN_HL, DELAY(-1,16ns,20ns),
+          DELAY(-1,24ns,36ns))}
U4CON CONSTRAINT(8) DPWR DGND
+     CLK CLRBAR 1PREBAR 2PREBAR 1J 1K 2J 2K
+     IO_H IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=10ns
+     MIN_LO=15ns
+
+  WIDTH:
+     NODE=CLRBAR
+     MIN_LO=16ns
+
+  WIDTH:
+     NODE=1PREBAR
+     MIN_LO=16ns
+
+  WIDTH:
+     NODE=2PREBAR
+     MIN_LO=16ns
+
+  SETUP_HOLD:
+     CLOCK HL=CLK
+     DATA(2)= 1J 1K
+     SETUPTIME_HI=10ns
+     SETUPTIME_LO=13ns
+     WHEN={1PREBAR!='0 & CLRBAR!='0}
+
+  SETUP_HOLD:
+     CLOCK HL=CLK
+     DATA(2)= 2J 2K
+     SETUPTIME_HI=10ns
+     SETUPTIME_LO=13ns
+     WHEN={2PREBAR!='0 & CLRBAR!='0}
+
.ENDS 74H108


.SUBCKT 74109 1PREBAR 1CLRBAR 1CLK 1J 1KBAR 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inva(2) DPWR DGND
+     1CLK 1KBAR 1CLKBAR 1K
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLKBAR 1J 1K 1Q_O 1QBAR_O
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3DLY PINDLY(2,0,3) DPWR DGND
+     1Q_O 1QBAR_O
+     1PREBAR 1CLRBAR 1CLK
+     1Q 1QBAR
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     PRE = {CHANGED_HL(1PREBAR,0)}
+     CLR = {CHANGED_HL(1CLRBAR,0)}
+     CLOCK = {CHANGED_LH(1CLK,0)}
+
+  PINDLY:
+     1Q 1QBAR = {
+       CASE(
+          CLOCK & TRN_LH, DELAY(-1,10ns,16ns),
+          (PRE | CLR) & TRN_LH, DELAY(-1,10ns,15ns),
+          PRE & TRN_HL, DELAY(-1,23ns,35ns),
+          CLOCK & TRN_HL, DELAY(-1,18ns,28ns),
+          CLR & TRN_HL, DELAY(-1,17ns,25ns),
+          DELAY(-1,24ns,36ns))}
U4CON CONSTRAINT(5) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1J 1KBAR
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=1CLK
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=1PREBAR
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=1CLRBAR
+     MIN_LO=20ns
+
+  SETUP_HOLD:
+     CLOCK LH=1CLK
+     DATA(2)=1J 1KBAR
+     SETUPTIME=10ns
+     HOLDTIME=6ns
.ENDS 74109


.SUBCKT 74AC109 SD1BAR CD1BAR CP1 J1 K1BAR Q1 Q1BAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inva(2) DPWR DGND
+     CP1 K1BAR CP1BAR K1
+     D0_GATE IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     SD1BAR CD1BAR CP1BAR J1 K1 Q1 Q1BAR
+     DLY_AC109 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AC109 ueff (tppcqlhMN=2.5ns tppcqlhTY=6ns tppcqlhMX=9ns
+                                tppcqhlMN=2ns tppcqhlTY=7.5ns tppcqhlMX=9.5ns
+                                tpclkqlhMN=2.5ns tpclkqlhTY=6ns tpclkqlhMX=10ns
+                                tpclkqhlMN=2ns tpclkqhlTY=6ns tpclkqhlMX=10ns
+                                twpclMN=3.5ns tsudclkMN=5ns thdclkMN=.5ns)
.ENDS 74AC109


.SUBCKT 74ACT109 SD1BAR CD1BAR CP1 J1 K1BAR Q1 Q1BAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inva(2) DPWR DGND
+     CP1 K1BAR CP1BAR K1
+     D0_GATE IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     SD1BAR CD1BAR CP1BAR J1 K1 Q1 Q1BAR
+     DLY_ACT109 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT109 ueff (tppcqlhMN=2.5ns tppcqlhTY=5.5ns tppcqlhMX=9.5ns
+                                tppcqhlMN=2.5ns tppcqhlTY=6ns tppcqhlMX=10ns
+                                tpclkqlhMN=4ns tpclkqlhTY=7ns tpclkqlhMX=11ns
+                                tpclkqhlMN=3ns tpclkqhlTY=6ns tpclkqhlMX=10ns
+                                twpclMN=6ns tsudclkMN=2.5ns thdclkMN=2ns)
.ENDS 74ACT109


.SUBCKT 74ALS109A 1PREBAR 1CLRBAR 1CLK 1J 1KBAR 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inva(2) DPWR DGND
+     1CLK 1KBAR CLKBAR 1K
+     D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR CLKBAR 1J 1K 1Q 1QBAR
+     DLY_ALS109 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS109 ueff (tppcqlhMN=3ns tppcqlhMX=13ns tppcqhlMN=5ns
+                                tppcqhlMX=15ns tpclkqlhMN=5ns tpclkqlhMX=16ns
+                                tpclkqhlMN=5ns tpclkqhlMX=18ns twclklMN=14.5ns twclkhMN=14.5ns
+                                twpclMN=15ns tsudclkMN=15ns tsupcclkhMN=10ns)
.ENDS 74ALS109A


.SUBCKT 74AS109 1PREBAR 1CLRBAR 1CLK 1J 1KBAR 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inva(2) DPWR DGND
+     1CLK 1KBAR CLKBAR 1K
+     D0_GATE IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR CLKBAR 1J 1K 1Q 1QBAR
+     DLY_AS109 IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS109 ueff (tppcqlhMN=3ns tppcqlhMX=8ns tppcqhlMN=3.5ns
+                                tppcqhlMX=10.5ns tpclkqlhMN=3.5ns tpclkqlhMX=9ns
+                                tpclkqhlMN=4.5ns tpclkqhlMX=9ns twclklMN=5.5ns twclkhMN=4ns
+                                twpclMN=4ns tsudclkMN=5.5ns tsupcclkhMN=2ns)
.ENDS 74AS109


.SUBCKT 74F109 1PREBAR 1CLRBAR 1CLK 1J 1KBAR 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inva(2) DPWR DGND
+     1CLK 1KBAR CLKBAR 1K
+     D0_GATE IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR CLKBAR 1J 1K 1Q 1QBAR
+     DLY_F109 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_F109 ueff (tppcqlhMN=2.4ns tppcqlhTY=4.8ns tppcqlhMX=7ns tppcqhlMN=2.7ns
+                                tppcqhlTY=6.6ns tppcqhlMX=9ns tpclkqlhMN=3ns tpclkqlhTY=4.9ns
+                                tpclkqlhMX=7ns tpclkqhlMN=3.6ns tpclkqhlTY=5.8ns tpclkqhlMX=8ns
+                                twclklMN=5ns twclkhMN=4ns twpclMN=4ns 
+                                tsudclkMN=3ns tsupcclkhMN=2ns thdclkMN=1ns)
.ENDS 74F109


.SUBCKT 74HC109 1PREBAR 1CLRBAR 1CLK 1J 1KBAR 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inva(2) DPWR DGND
+     1CLK 1KBAR CLKBAR 1K
+     D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR CLKBAR 1J 1K 1Q 1QBAR
+     DLY_HC109 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC109 ueff (tppcqlhTY=15ns tppcqlhMX=46ns tppcqhlTY=15ns
+                                tppcqhlMX=46ns tpclkqlhTY=15ns tpclkqlhMX=35ns
+                                tpclkqhlTY=15ns tpclkqhlMX=35ns twclklMN=20ns twclkhMN=20ns
+                                twpclMN=25ns tsudclkMN=25ns tsupcclkhMN=6ns)
.ENDS 74HC109


.SUBCKT 74HCT109 1SDBAR 1RDBAR 1CP 1J 1KBAR 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inva(2) DPWR DGND
+     1CP 1KBAR CPBAR 1K
+     D0_GATE IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     1SDBAR 1RDBAR CPBAR 1J 1K 1Q_O 1QBAR_O
+     D0_EFF IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3DLY PINDLY(2,0,3) DPWR DGND
+     1Q_O 1QBAR_O
+     1SDBAR 1RDBAR 1CP
+     1Q 1QBAR
+     IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     CLOCK = {CHANGED_LH(1CP,0)}
+     SET = {CHANGED_HL(1SDBAR,0)}
+     RESET = {CHANGED_HL(1RDBAR,0)}
+
+  PINDLY:
+     1Q = {
+       CASE(
+         SET & TRN_LH, DELAY(-1,13ns,26ns),
+         RESET & TRN_HL, DELAY(-1,19ns,35ns),
+         CLOCK, DELAY(-1,20ns,35ns),
+         DELAY(-1,21ns,36ns))}
+
+     1QBAR = {
+       CASE(
+         SET & TRN_HL, DELAY(-1,19ns,35ns),
+         RESET & TRN_LH, DELAY(-1,16ns,32ns),
+         CLOCK, DELAY(-1,20ns,35ns),
+         DELAY(-1,21ns,36ns))}
U4CON CONSTRAINT(5) DPWR DGND
+     1SDBAR 1RDBAR 1CP 1J 1KBAR
+     IO_HCT IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=1CP
+     MIN_HI=23ns
+     MIN_LO=23ns
+
+  WIDTH:
+     NODE=1SDBAR
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  WIDTH:
+     NODE=1RDBAR
+     MIN_HI=20ns
+     MIN_LO=20ns
+
+  FREQ:
+     NODE=1CP
+     MAXFREQ=22MEG
+
+  SETUP_HOLD:
+     CLOCK LH=1CP
+     DATA(2)=1SDBAR 1RDBAR
+     SETUPTIME_HI=20ns
+
+  SETUP_HOLD:
+     CLOCK LH=1CP
+     DATA(2)=1J 1KBAR
+     SETUPTIME=23ns
+     HOLDTIME=3ns
+     WHEN = {1SDBAR!='0 | 1RDBAR!='0}
.ENDS 74HCT109


.SUBCKT 74LS109A 1PREBAR 1CLRBAR 1CLK 1J 1KBAR 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inva(2) DPWR DGND
+     1CLK 1KBAR CLKBAR 1K
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR CLKBAR 1J 1K 1Q 1QBAR
+     DLY_LS109 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3CON CONSTRAINT(3) DPWR DGND
+     1J 1KBAR 1CLK
+     IO_LS IO_LEVEL={IO_LEVEL}
+
+  SETUP_HOLD:
+     CLOCK LH=1CLK
+     DATA(2)=1J 1KBAR
+     SETUPTIME_HI=35ns
+     SETUPTIME_LO=25ns
.model DLY_LS109 ueff (tppcqlhTY=13ns tppcqlhMX=25ns tppcqhlTY=25ns
+                                tppcqhlMX=40ns tpclkqlhTY=13ns tpclkqlhMX=25ns
+                                tpclkqhlTY=25ns tpclkqhlMX=40ns twclkhMN=25ns
+                                twpclMN=25ns thdclkMN=5ns)
.ENDS 74LS109A


.SUBCKT 74S109 SD1BAR CD1BAR CP1 J1 K1BAR Q1 Q1BAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inva(2) DPWR DGND
+     CP1 K1BAR CP1BAR K1
+     D0_GATE IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     SD1BAR CD1BAR CP1BAR J1 K1 Q1 Q1BAR
+     DLY_S109 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S109 ueff (tppcqlhMX=6ns tppcqhlMX=11ns tpclkqlhMX=9ns
+                                tpclkqhlMX=11ns twpclMN=6ns twclklMN=6.5ns
+                                twclkhMN=7ns tsudclkMN=6ns)
.ENDS 74S109


.SUBCKT 74110 PREBAR CLRBAR CLK J1 J2 J3 K1 K2 K3 Q QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 anda(3,2) DPWR DGND
+     J1 J2 J3 K1 K2 K3 J K
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 inv DPWR DGND
+     CLK CLKBAR
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     PREBAR CLRBAR CLKBAR J K MQ MQBAR
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+     PREBAR CLRBAR CLK MQ MQBAR Q_O QBAR_O
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5DLY PINDLY(2,0,3) DPWR DGND
+     Q_O QBAR_O
+     PREBAR CLRBAR CLK
+     Q QBAR
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     PCL = {CHANGED_HL(PREBAR,0) | CHANGED_HL(CLRBAR,0)}
+     CLOCK = {CHANGED(CLK,0)}
+
+  PINDLY:
+     Q QBAR = {
+       CASE(
+          PCL & TRN_LH, DELAY(-1,12ns,20ns),
+          PCL & TRN_HL, DELAY(-1,18ns,25ns),
+          CLOCK & TRN_LH, DELAY(-1,20ns,30ns),
+          CLOCK & TRN_HL, DELAY(-1,13ns,20ns),
+          DELAY(-1,21ns,31ns))}
U6CON CONSTRAINT(5) DPWR DGND
+     PREBAR CLRBAR CLK J K
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=CLK
+     MIN_HI=25ns
+     MIN_LO=25ns
+
+  WIDTH:
+     NODE=PREBAR
+     MIN_LO=25ns
+
+  WIDTH:
+     NODE=CLRBAR
+     MIN_LO=25ns
+
+  SETUP_HOLD:
+     CLOCK LH=CLK
+     DATA(2)=J K
+     SETUPTIME=20ns
+     HOLDTIME=5ns
+     WHEN= {PREBAR!='0 & CLRBAR!='0}
.ENDS 74110


.SUBCKT 74111 1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1CLK CLKBAR
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR CLKBAR 1J 1K MQ MQBAR
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK MQ MQBAR 1Q_O 1QBAR_O
+     D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4DLY PINDLY(2,0,3) DPWR DGND
+     1Q_O 1QBAR_O
+     1PREBAR 1CLRBAR 1CLK
+     1Q 1QBAR
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     PCL = {CHANGED_HL(1PREBAR,0) | CHANGED_HL(1CLRBAR,0)}
+     CLOCK = {CHANGED(1CLK,0)}
+
+  PINDLY:
+     1Q 1QBAR = {
+       CASE(
+          PCL & TRN_LH, DELAY(-1,12ns,18ns),
+          PCL & TRN_HL, DELAY(-1,21ns,30ns),
+          CLOCK & TRN_LH, DELAY(-1,12ns,17ns),
+          CLOCK & TRN_HL, DELAY(-1,20ns,30ns),
+          DELAY(-1,22ns,31ns))}
U6CON CONSTRAINT(5) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1J 1K
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=1CLK
+     MIN_HI=25ns
+     MIN_LO=25ns
+
+  WIDTH:
+     NODE=1PREBAR
+     MIN_LO=25ns
+
+  WIDTH:
+     NODE=1CLRBAR
+     MIN_LO=25ns
+
+  SETUP_HOLD:
+     CLOCK LH=1CLK
+     DATA(2)=1J 1K
+     HOLDTIME=30ns
+     WHEN= {1PREBAR!='0 & 1CLRBAR!='0}
.ENDS 74111


.SUBCKT 74AC112 1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     DLY_AC112 IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AC112 ueff (tppcqlhMN=1.5ns tppcqlhTY=3.3ns tppcqlhMX=5.1ns
+                              tppcqhlMN=1.5ns tppcqhlTY=4.6ns tppcqhlMX=6.7ns
+                              tpclkqlhMN=1.5ns tpclkqlhTY=3.4ns tpclkqlhMX=5.1ns
+                              tpclkqhlMN=1.5ns tpclkqhlTY=4.2ns tpclkqhlMX=6.3ns
+                              twpclMN=4ns twclklMN=4ns twclkhMN=4ns tsupcclkhMN=2ns
+                              tsudclkMN=3.5ns thdclkMN=1ns)
.ENDS 74AC112


.SUBCKT 74ACT112 1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     DLY_ACT112 IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ACT112 ueff (tppcqlhMN=1.5ns tppcqlhTY=3.6ns tppcqlhMX=6.3ns
+                              tppcqhlMN=1.5ns tppcqhlTY=4.6ns tppcqhlMX=7.4ns
+                              tpclkqlhMN=1.5ns tpclkqlhTY=4.2ns tpclkqlhMX=7ns
+                              tpclkqhlMN=1.5ns tpclkqhlTY=4.7ns tpclkqhlMX=7.4ns
+                              twpclMN=4ns twclklMN=4ns twclkhMN=4ns tsupcclkhMN=2ns
+                              tsudclkMN=4.5ns thdclkMN=1.5ns)
.ENDS 74ACT112


.SUBCKT 74ALS112A 1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     DLY_ALS112 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS112 ueff (tppcqlhMN=3ns tppcqlhMX=15ns
+                              tppcqhlMN=4ns tppcqhlMX=18ns
+                              tpclkqlhMN=3ns tpclkqlhMX=15ns
+                              tpclkqhlMN=5ns tpclkqhlMX=19ns
+                              twpclMN=10ns twclklMN=16.5ns twclkhMN=16.5ns
+                              tsupcclkhMN=20ns tsudclkMN=22ns)
.ENDS 74ALS112A


.SUBCKT 74F112 1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     DLY_F112 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2CON CONSTRAINT(5) DPWR DGND
+     1J 1K 1CLK 1PREBAR 1CLRBAR
+     IO_F IO_LEVEL={IO_LEVEL}
+
+  SETUP_HOLD:
+     CLOCK HL=1CLK
+     DATA(2)=1J 1K
+     SETUPTIME_HI=5ns
+     SETUPTIME_LO=3.5ns
+     WHEN= {1PREBAR!='0 & 1CLRBAR!='0}
.model DLY_F112 ueff (tppcqlhMN=1.2ns tppcqlhTY=4.1ns tppcqlhMX=6.5ns
+                              tppcqhlMN=1.2ns tppcqhlTY=4.1ns tppcqhlMX=6.5ns
+                              tpclkqlhMN=1.2ns tpclkqlhTY=4.6ns tpclkqlhMX=6.5ns
+                              tpclkqhlMN=1.2ns tpclkqhlTY=4.6ns tpclkqhlMX=6.5ns
+                              twpclMN=5ns twclklMN=5ns twclkhMN=5ns tsupcclkhMN=5ns)
.ENDS 74F112


.SUBCKT 74HC112 1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     DLY_HC112 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC112 ueff (tppcqlhTY=16ns tppcqlhMX=33ns
+                              tppcqhlTY=16ns tppcqhlMX=33ns
+                              tpclkqlhTY=16ns tpclkqlhMX=25ns
+                              tpclkqhlTY=16ns tpclkqhlMX=25ns
+                              twpclMN=25ns twclklMN=25ns twclkhMN=25ns
+                              tsudclkMN=25ns tsupcclkhMN=25ns)
.ENDS 74HC112


.SUBCKT 74HCT112 1SDBAR 1RDBAR 1CP 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1SDBAR 1RDBAR 1CP 1J 1K 1Q_O 1QBAR_O
+     DLY_HCT112 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(2,0,3) DPWR DGND
+     1Q_O 1QBAR_O
+     1SDBAR 1RDBAR 1CP
+     1Q 1QBAR
+     IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     CLOCK = {CHANGED_HL(1CP,0)}
+     SET = {CHANGED_HL(1SDBAR,0)}
+     RESET = {CHANGED_HL(1RDBAR,0)}
+
+  PINDLY:
+     1Q = {
+       CASE(
+         RESET, DELAY(-1,22ns,37ns),
+         SET, DELAY(-1,18ns,32ns),
+         CLOCK, DELAY(-1,21ns,35ns),
+         DELAY(-1,23ns,38ns))}
+
+     1QBAR = {
+       CASE(
+         RESET, DELAY(-1,22ns,37ns),
+         SET, DELAY(-1,18ns,32ns),
+         CLOCK, DELAY(-1,23ns,40ns),
+         DELAY(-1,23ns,41ns))}
.model DLY_HCT112 ueff (twpclMN=23ns twclklMN=20ns twclkhMN=20ns
+                                tsupcclkhMN=25ns tsudclkMN=20ns)
.ENDS 74HCT112


.SUBCKT 74LS112A 1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     DLY_LS112 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2CON CONSTRAINT(3) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK
+     IO_LS IO_LEVEL={IO_LEVEL}
+
+  SETUP_HOLD:
+     CLOCK HL=1CLK
+     DATA(1)=1PREBAR
+     SETUPTIME_HI=20ns
+
+  SETUP_HOLD:
+     CLOCK HL=1CLK
+     DATA(1)=1CLRBAR
+     SETUPTIME_HI=25ns
.model DLY_LS112 ueff (tppcqlhTY=15ns tppcqlhMX=20ns
+                              tppcqhlTY=15ns tppcqhlMX=20ns
+                              tpclkqlhTY=15ns tpclkqlhMX=20ns
+                              tpclkqhlTY=15ns tpclkqhlMX=20ns
+                              twpclMN=25ns twclkhMN=20ns tsudclkMN=20ns)
.ENDS 74LS112A


.SUBCKT 74S112 1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR 1CLRBAR 1CLK 1J 1K 1Q 1QBAR
+     DLY_S112 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S112 ueff (tppcqlhTY=4ns tppcqlhMX=7ns
+                              tppcqhlTY=5ns tppcqhlMX=7ns
+                              tpclkqlhTY=4ns tpclkqlhMX=7ns
+                              tpclkqhlTY=5ns tpclkqhlMX=7ns twclklMN=6.5ns
+                              twpclMN=8ns twclkhMN=6ns tsudclkMN=7ns)
.ENDS 74S112


.SUBCKT 74AC113
+ J K CPBAR SDBAR Q QBAR
+ OPTIONAL:  DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+ SDBAR $D_HI CPBAR
+ J K QO QBARO
+ D0_EFF IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(2,0,2) DPWR DGND
+ QO QBARO
+ CPBAR SDBAR
+ Q QBAR
+ IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+          EDGE = {CHANGED_HL(CPBAR,0)}
+          SET = {CHANGED_HL(SDBAR,0)}
+ PINDLY:
+          Q = {
+            CASE(
+              SET & TRN_LH, DELAY(1NS,-1,9NS),
+              EDGE & TRN_LH, DELAY(1NS,-1,12NS),
+              EDGE & TRN_HL, DELAY(1NS,-1,12.5NS),
+              DELAY(2NS,-1,13.5NS))}
+          QBAR = {
+            CASE(
+              SET & TRN_HL, DELAY(1NS,-1,11NS),
+              EDGE & TRN_LH, DELAY(1NS,-1,12NS),
+              EDGE & TRN_HL, DELAY(1NS,-1,12.5NS),
+              DELAY(2NS,-1,13.5NS))}
U3 CONSTRAINT(4) DPWR DGND
+ CPBAR J K SDBAR
+ IO_AC IO_LEVEL={IO_LEVEL}
+ SETUP_HOLD:
+             CLOCK HL = CPBAR
+             DATA(2) = J K
+             SETUPTIME = 4.5NS
+ WIDTH:
+             NODE = CPBAR
+             MIN_LO = 4NS
+             MIN_HI = 4NS
+ WIDTH:
+             NODE = SDBAR
+             MIN_LO = 5NS
+ FREQ:
+             NODE = CPBAR
+             MAXFREQ = 145MEG
.ENDS 74AC113


.SUBCKT 74ACT113
+ J K CPBAR SDBAR Q QBAR
+ OPTIONAL:  DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+ SDBAR $D_HI CPBAR
+ J K QO QBARO
+ D0_EFF IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(2,0,2) DPWR DGND
+ QO QBARO
+ CPBAR SDBAR
+ Q QBAR
+ IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+          EDGE = {CHANGED_HL(CPBAR,0)}
+          SET = {CHANGED_HL(SDBAR,0)}
+ PINDLY:
+          Q = {
+            CASE(
+              SET & TRN_LH, DELAY(1NS,-1,11.5NS),
+              EDGE & TRN_LH, DELAY(1NS,-1,14NS),
+              EDGE & TRN_HL, DELAY(1NS,-1,13.5NS),
+              DELAY(2NS,-1,15NS))}
+          QBAR = {
+            CASE(
+              SET & TRN_HL, DELAY(1NS,-1,13NS),
+              EDGE & TRN_LH, DELAY(1NS,-1,14NS),
+              EDGE & TRN_HL, DELAY(1NS,-1,13.5NS),
+              DELAY(2NS,-1,15NS))}
U3 CONSTRAINT(4) DPWR DGND
+ CPBAR J K SDBAR
+ IO_ACT IO_LEVEL={IO_LEVEL}
+ SETUP_HOLD:
+             CLOCK HL = CPBAR
+             DATA(2) = J K
+             SETUPTIME = 2NS
+             HOLDTIME = 2NS
+ WIDTH:
+             NODE = CPBAR
+             MIN_LO = 5NS
+             MIN_HI = 5NS
+ WIDTH:
+             NODE = SDBAR
+             MIN_LO = 5.5NS
+ FREQ:
+             NODE = CPBAR
+             MAXFREQ = 145MEG
.ENDS 74ACT113


.SUBCKT 74ALS113A 1PREBAR 1J 1CLK 1K 1Q 1QBAR
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+ 1PREBAR $D_HI 1CLK
+ 1J 1K 1QO 1QBARO
+ D0_EFF IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(2,0,2) DPWR DGND
+ 1QO 1QBARO
+ 1PREBAR 1CLK
+ 1Q 1QBAR
+ IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+    SET = {CHANGED(1PREBAR,0)}
+    EDGE = {CHANGED_HL(1CLK,0)}
+ PINDLY:
+    1Q 1QBAR = {
+      CASE(
+        SET & TRN_LH, DELAY(3NS,-1,14NS),
+        SET & TRN_HL, DELAY(4NS,-1,16NS),
+        EDGE & TRN_LH, DELAY(3NS,-1,15NS),
+        EDGE & TRN_HL, DELAY(5NS,-1,19NS),
+        DELAY(6NS,-1,20NS))}
U3 CONSTRAINT(4) DPWR DGND
+ 1CLK 1PREBAR 1J 1K
+ IO_ALS00 IO_LEVEL={IO_LEVEL}
+ FREQ:
+   NODE = 1CLK
+   MAXFREQ = 30MEG
+ WIDTH:
+   NODE = 1CLK
+   MIN_LO = 16.5NS
+   MIN_HI = 16.5NS
+ WIDTH:
+   NODE = 1PREBAR
+   MIN_LO = 10NS
+ SETUP_HOLD:
+   CLOCK HL = 1CLK
+   DATA(2) = 1J 1K
+   SETUPTIME = 22NS
+ SETUP_HOLD:
+   CLOCK HL = 1CLK
+   DATA(1) = 1PREBAR
+   SETUPTIME_HI = 20NS
.ENDS 74ALS113A


.SUBCKT 74F113
+ J K CPBAR SDBAR Q QBAR
+ OPTIONAL:  DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+ SDBAR $D_HI CPBAR
+ J K Q_ Q_BAR
+ D0_EFF IO_F
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(2,0,2) DPWR DGND
+ Q_ Q_BAR
+ CPBAR SDBAR
+ Q QBAR
+ IO_F
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+          EDGE = {CHANGED_HL(CPBAR,0)}
+          SET = {CHANGED_HL(SDBAR,0)}
+ PINDLY:
+          Q QBAR = {
+            CASE(
+              SET & (TRN_LH | TRN_HL), DELAY(2NS,4.5NS,6.5NS),
+              EDGE & (TRN_LH | TRN_HL), DELAY(2NS,4NS,6NS),
+              DELAY(3NS,5.5NS,7.5NS))}
U3 CONSTRAINT(4) DPWR DGND
+ CPBAR J K SDBAR
+ IO_F IO_LEVEL={IO_LEVEL}
+ SETUP_HOLD:
+             CLOCK HL = CPBAR
+             DATA(2) = J K
+             SETUPTIME_LO = 4NS
+             SETUPTIME_HI = 5NS
+ WIDTH:
+             NODE = CPBAR
+             MIN_LO = 5NS
+             MIN_HI = 5NS
+ WIDTH:
+             NODE = SDBAR
+             MIN_LO = 5NS
+ SETUP_HOLD:
+             CLOCK HL = CPBAR
+             DATA(1) = SDBAR
+             SETUPTIME_HI = 5NS
+ FREQ:
+             NODE = CPBAR
+             MAXFREQ = 80MEG
.ENDS 74F113


.SUBCKT 74HC113 1PREBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR $D_HI 1CLK 1J 1K 1Q 1QBAR
+     DLY_HC113 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC113 ueff (tppcqlhTY=18ns tppcqlhMX=33ns
+                              tppcqhlTY=18ns tppcqhlMX=33ns
+                              tpclkqlhTY=19ns tpclkqlhMX=28ns
+                              tpclkqhlTY=19ns tpclkqhlMX=28ns
+                              twpclMN=25ns twclklMN=20ns twclkhMN=20ns
+                              tsudclkMN=25ns tsupcclkhMN=6ns)
.ENDS 74HC113


.SUBCKT 74LS113A 1PREBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR $D_HI 1CLK 1J 1K 1Q 1QBAR
+     DLY_LS113 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS113 ueff (tppcqlhTY=15ns tppcqlhMX=20ns
+                              tppcqhlTY=15ns tppcqhlMX=20ns
+                              tpclkqlhTY=15ns tpclkqlhMX=20ns
+                              tpclkqhlTY=15ns tpclkqhlMX=20ns tsupcclkhMN=20ns
+                              twpclMN=25ns twclkhMN=20ns tsudclkMN=20ns)
.ENDS 74LS113A


.SUBCKT 74S113 1PREBAR 1CLK 1J 1K 1Q 1QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR $D_HI 1CLK 1J 1K 1Q 1QBAR
+     DLY_S113 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S113 ueff (tppcqlhTY=4ns tppcqlhMX=7ns
+                              tppcqhlTY=5ns tppcqhlMX=7ns
+                              tpclkqlhTY=4ns tpclkqlhMX=7ns
+                              tpclkqhlTY=5ns tpclkqhlMX=7ns twclklMN=6.5ns
+                              twpclMN=8ns twclkhMN=6ns tsudclkMN=7ns)
.ENDS 74S113


.SUBCKT 74ALS114A 1PREBAR 1J 1K 1Q 1QBAR 2PREBAR 2J 2K 2Q 2QBAR CLK CLRBAR
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+ 1PREBAR CLRBAR CLK
+ 1J 1K 1QO 1QBARO
+ D0_EFF IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U1A JKFF(1) DPWR DGND
+ 2PREBAR CLRBAR CLK
+ 2J 2K 2QO 2QBARO
+ D0_EFF IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 PINDLY(4,0,4) DPWR DGND
+ 1QO 1QBARO 2QO 2QBARO
+ 1PREBAR CLK 2PREBAR CLRBAR
+ 1Q 1QBAR 2Q 2QBAR
+ IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+    SET1 = {CHANGED(1PREBAR,0)}
+    SET2 = {CHANGED(2PREBAR,0)}
+    EDGE = {CHANGED_HL(CLK,0)}
+    CLEAR = {CHANGED(CLRBAR,0)}
+ PINDLY:
+    1Q 1QBAR = {
+      CASE(
+        SET1 & TRN_LH, DELAY(3NS,-1,15NS),
+        SET1 & TRN_HL, DELAY(4NS,-1,18NS),
+        CLEAR & TRN_LH, DELAY(3NS,-1,15NS),
+        CLEAR & TRN_HL, DELAY(4NS,-1,18NS),
+        EDGE & TRN_LH, DELAY(3NS,-1,15NS),
+        EDGE & TRN_HL, DELAY(5NS,-1,19NS),
+        DELAY(6NS,-1,20NS))}
+    2Q 2QBAR = {
+      CASE(
+        SET2 & TRN_LH, DELAY(3NS,-1,15NS),
+        SET2 & TRN_HL, DELAY(4NS,-1,18NS),
+        CLEAR & TRN_LH, DELAY(3NS,-1,15NS),
+        CLEAR & TRN_HL, DELAY(4NS,-1,18NS),
+        EDGE & TRN_LH, DELAY(3NS,-1,15NS),
+        EDGE & TRN_HL, DELAY(5NS,-1,19NS),
+        DELAY(6NS,-1,20NS))}
U3 CONSTRAINT(8) DPWR DGND
+ CLK CLRBAR 1PREBAR 2PREBAR 1J 1K 2J 2K
+ IO_ALS00 IO_LEVEL={IO_LEVEL}
+ FREQ:
+   NODE = CLK
+   MAXFREQ = 30MEG
+ WIDTH:
+   NODE = CLK
+   MIN_LO = 16.5NS
+   MIN_HI = 16.5NS
+ WIDTH:
+   NODE = 1PREBAR
+   MIN_LO = 10NS
+ WIDTH:
+   NODE = 2PREBAR
+   MIN_LO = 10NS
+ WIDTH:
+   NODE = CLRBAR
+   MIN_LO = 10NS
+ SETUP_HOLD:
+   CLOCK HL = CLK
+   DATA(4) = 1J 2J 1K 2K
+   SETUPTIME = 22NS
+ SETUP_HOLD:
+   CLOCK HL = CLK
+   DATA(3) = 1PREBAR 2PREBAR CLRBAR
+   SETUPTIME_HI = 20NS
.ENDS 74ALS114A


.SUBCKT 74F114
+ J0 K0 J1 K1 CPBAR SD0BAR SD1BAR RDBAR Q0 Q0BAR Q1 Q1BAR
+ OPTIONAL:  DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+ SD0BAR RDBAR CPBAR
+ J0 K0 Q_0 Q_0BAR
+ D0_EFF IO_F
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+ SD1BAR RDBAR CPBAR
+ J1 K1 Q_1 Q_1BAR
+ D0_EFF IO_F
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2A PINDLY(4,0,4) DPWR DGND
+ Q_0 Q_1 Q_0BAR Q_1BAR
+ CPBAR SD0BAR SD1BAR RDBAR
+ Q0 Q1 Q0BAR Q1BAR
+ IO_F
+ MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+          EDGE = {CHANGED_HL(CPBAR,0)}
+          SET = {CHANGED_HL(SD0BAR,0) | CHANGED_HL(SD1BAR,0) |
+                 CHANGED_HL(RDBAR,0)}
+ PINDLY:
+          Q0 Q1 Q0BAR Q1BAR = {
+            CASE(
+              SET & (TRN_LH | TRN_HL), DELAY(2NS,4.5NS,6.5NS),
+              EDGE & TRN_LH, DELAY(2NS,5NS,6.5NS),
+              EDGE & TRN_HL, DELAY(2NS,5.5NS,7.5NS),
+              DELAY(3NS,6.5NS,8.5NS))}
U3 CONSTRAINT(8) DPWR DGND
+ CPBAR J0 J1 K0 K1 SD0BAR SD1BAR RDBAR
+ IO_F IO_LEVEL={IO_LEVEL}
+ SETUP_HOLD:
+             CLOCK HL = CPBAR
+             DATA(4) = J0 J1 K0 K1
+             SETUPTIME_LO = 5NS
+             SETUPTIME_HI = 4NS
+ WIDTH:
+             NODE = CPBAR
+             MIN_LO = 5NS
+             MIN_HI = 5NS
+ WIDTH:
+             NODE = SD0BAR
+             MIN_LO = 5NS
+ WIDTH:
+             NODE = SD1BAR
+             MIN_LO = 5NS
+ WIDTH:
+             NODE = RDBAR
+             MIN_LO = 5NS
+ SETUP_HOLD:
+             CLOCK HL = CPBAR
+             DATA(3) = SD0BAR SD1BAR RDBAR
+             SETUPTIME_HI = 5NS
+ FREQ:
+             NODE = CPBAR
+             MAXFREQ = 80MEG
.ENDS 74F114


.SUBCKT 74HC114 CLRBAR CLK 1PREBAR 1J 1K 2PREBAR 2J 2K 1Q 1QBAR 2Q 2QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR CLRBAR CLK 1J 1K 1Q 1QBAR
+     DLY_HC114 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     2PREBAR CLRBAR CLK 2J 2K 2Q 2QBAR
+     DLY_HC114 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC114 ueff (tppcqlhTY=20ns tppcqlhMX=35ns tppcqhlTY=20ns
+                               tppcqhlMX=35ns tpclkqlhTY=19ns tpclkqlhMX=35ns
+                               tpclkqhlTY=19ns tpclkqhlMX=35ns twpclMN=25ns
+                               twclklMN=25ns twclkhMN=25ns tsudclkMN=25ns tsupcclkhMN=25ns)
.ENDS 74HC114


.SUBCKT 74LS114A CLRBAR CLK 1PREBAR 1J 1K 2PREBAR 2J 2K 1Q 1QBAR 2Q 2QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR CLRBAR CLK 1J 1K 1Q 1QBAR
+     DLY_LS114 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     2PREBAR CLRBAR CLK 2J 2K 2Q 2QBAR
+     DLY_LS114 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3CON CONSTRAINT(4) DPWR DGND
+     CLRBAR 1PREBAR 2PREBAR CLK
+     IO_LS IO_LEVEL={IO_LEVEL}
+
+  SETUP_HOLD:
+     CLOCK HL=CLK
+     DATA(1)=CLRBAR
+     SETUPTIME_HI=25ns
+
+  SETUP_HOLD:
+     CLOCK HL=CLK
+     DATA(1)=1PREBAR
+     SETUPTIME_HI=20ns
+
+  SETUP_HOLD:
+     CLOCK HL=CLK
+     DATA(1)=2PREBAR
+     SETUPTIME_HI=20ns
.model DLY_LS114 ueff (tppcqlhTY=15ns tppcqlhMX=20ns tppcqhlTY=15ns
+                               tppcqhlMX=20ns tpclkqlhTY=15ns tpclkqlhMX=20ns
+                               tpclkqhlTY=15ns tpclkqhlMX=20ns twpclMN=25ns
+                               twclklMN=20ns twclkhMN=20ns tsudclkMN=20ns)
.ENDS 74LS114A


.SUBCKT 74S114 CLRBAR CLK 1PREBAR 1J 1K 2PREBAR 2J 2K 1Q 1QBAR 2Q 2QBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 JKFF(1) DPWR DGND
+     1PREBAR CLRBAR CLK 1J 1K 1Q 1QBAR
+     DLY_S114 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 JKFF(1) DPWR DGND
+     2PREBAR CLRBAR CLK 2J 2K 2Q 2QBAR
+     DLY_S114 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S114 ueff (tppcqlhTY=4ns tppcqlhMX=7ns tppcqhlTY=5ns
+                               tppcqhlMX=7ns tpclkqlhTY=4ns tpclkqlhMX=7ns
+                               tpclkqhlTY=5ns tpclkqhlMX=7ns twpclMN=8ns
+                               twclklMN=6.5ns twclkhMN=6ns tsudclkMN=7ns)
.ENDS 74S114


.SUBCKT 74116
+ CLRBAR C1BAR C2BAR D1 D2 D3 D4 Q1 Q2 Q3 Q4
+ OPTIONAL: DPWR = $G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(2,1) DPWR DGND
+ C1BAR C2BAR
+ GATE
+ D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+    GATE = {~C1BAR & ~C2BAR}
U2 DLTCH(4) DPWR DGND
+ $D_HI CLRBAR GATE
+ D1 D2 D3 D4
+ Q1O Q2O Q3O Q4O
+ $D_NC $D_NC $D_NC $D_NC
+ D0_GFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 PINDLY(4,0,7) DPWR DGND
+ Q1O Q2O Q3O Q4O
+ CLRBAR C1BAR C2BAR D1 D2 D3 D4
+ Q1 Q2 Q3 Q4
+ IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+   CLEAR = {CHANGED(CLRBAR,0)}
+   LATCH = {CHANGED(C1BAR,0) | CHANGED(C2BAR,0)}
+   DATA = {CHANGED(D1,0) | CHANGED(D2,0) | CHANGED(D3,0) | CHANGED(D4,0)}
+ PINDLY:
+   Q1 Q2 Q3 Q4  = {
+       CASE(
+          CLEAR & TRN_HL, DELAY(-1,15NS,22NS),
+          LATCH & TRN_LH, DELAY(-1,19NS,30NS),
+          LATCH & TRN_HL, DELAY(-1,15NS,22NS),
+           DATA & TRN_LH, DELAY(-1,10NS,15NS),
+           DATA & TRN_HL, DELAY(-1,12NS,18NS),
+           DELAY(-1,20NS,31NS))}
U4 CONSTRAINT(8) DPWR DGND
+ CLRBAR GATE C1BAR C2BAR D1 D2 D3 D4
+ IO_STD IO_LEVEL={IO_LEVEL}
+ WIDTH:
+   NODE = C1BAR
+   MIN_LO = 18NS
+   MIN_HI = 18NS
+ WIDTH:
+   NODE = C2BAR
+   MIN_LO = 18NS
+   MIN_HI = 18NS
+ WIDTH:
+   NODE = CLRBAR
+   MIN_LO = 18NS
+   MIN_HI = 18NS
+ SETUP_HOLD:
+   CLOCK HL = GATE
+   DATA(4) = D1 D2 D3 D4
+   SETUPTIME_HI = 8NS
+   SETUPTIME_LO = 14NS
+   HOLDTIME_HI = 2NS
+   HOLDTIME_LO = 8NS
+ SETUP_HOLD:
+   CLOCK HL = GATE
+   DATA(1) = CLRBAR
+   SETUPTIME_HI = 8NS
.ENDS 74116


.SUBCKT 74120 1RBAR 1S1BAR 1S2BAR 1C 1MBAR 1Y 1YBAR
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1C 1CBAR
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 nanda(3,5) DPWR DGND
+     1S1BAR 1S2BAR RNAND 1CBAR SNAND MNAND
+     SNAND MNAND FB3 CBNAND FBNAND 1YBAR_O
+     SNAND 1MBAR FB2
+     SNAND CBNAND FBNAND FB3 MNAND
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 nanda(2,3) DPWR DGND
+     1RBAR SNAND FB3 1C 1YBAR_O MNAND
+     RNAND 1YBAR_O FB2
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 inv DPWR DGND
+     1YBAR_O 1Y_O
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5DLY PINDLY(2,0,1) DPWR DGND
+     1Y_O 1YBAR_O
+     1C
+     1Y 1YBAR
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     1Y = {
+       CASE(
+          CHANGED(1C,0) & TRN_LH, DELAY(-1,14ns,22ns),
+          CHANGED(1C,0) & TRN_HL, DELAY(-1,17ns,25ns),
+          DELAY(-1,18ns,26ns))}
+
+     1YBAR = {
+       CASE(
+          CHANGED(1C,0) & TRN_LH, DELAY(-1,10ns,16ns),
+          CHANGED(1C,0) & TRN_HL, DELAY(-1,8ns, 13ns),
+          DELAY(-1,11ns,17ns))}
U6CON CONSTRAINT(5) DPWR DGND
+     1RBAR 1S1BAR 1S2BAR 1C 1MBAR
+     IO_STD IO_LEVEL={IO_LEVEL}
+
+  SETUP_HOLD:
+     CLOCK LH=1C
+     DATA(3)=1RBAR 1S1BAR 1S2BAR
+     SETUPTIME=12ns
+     HOLDTIME=3ns
+
+  SETUP_HOLD:
+     CLOCK LH=1C
+     DATA(1)=1MBAR
+     SETUPTIME_LO=12ns
+     HOLDTIME=20ns
.ENDS 74120


.SUBCKT 74125 1A 1GBAR 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1GBAR 1G
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 buf3 DPWR DGND
+     1A 1G 1Y
+     DLY_125 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_125 utgate (tplhTY=8ns tplhMX=13ns tphlTY=12ns tphlMX=18ns
+                               tplzTY=7ns tplzMX=12ns tphzTY=5ns tphzMX=8ns
+                               tpzlTY=16ns tpzlMX=25ns tpzhTY=11ns tpzhMX=17ns)
.ENDS 74125


.SUBCKT 74AC125 A0BAR B0 O0
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 PINDLY(1,1,0) DPWR DGND
+ B0
+ A0BAR
+ O0
+ IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ TRISTATE:
+ ENABLE LO = A0BAR
+  O0 = {
+    CASE(
+    TRN_ZH,DELAY(1NS,-1,7NS),
+    TRN_ZL, DELAY(1NS,-1,8NS),
+    TRN_HZ, DELAY(1NS,-1,9NS),
+    TRN_LZ, DELAY(1NS,-1,9NS),
+    TRN_LH, DELAY(1NS,-1,7NS),
+    TRN_HL, DELAY(1NS,-1,7NS),
+    DELAY(2NS,-1,10NS))}
.ENDS 74AC125


.SUBCKT 74ACT125 A0BAR B0 O0
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 PINDLY(1,1,0) DPWR DGND
+ B0
+ A0BAR
+ O0
+ IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ TRISTATE:
+ ENABLE LO = A0BAR
+  O0 = {
+    CASE(
+    TRN_ZH,DELAY(1NS,-1,8.5NS),
+    TRN_ZL, DELAY(1NS,-1,9.5NS),
+    TRN_HZ, DELAY(1NS,-1,9.5NS),
+    TRN_LZ, DELAY(1NS,-1,10NS),
+    TRN_LH, DELAY(1NS,-1,9NS),
+    TRN_HL, DELAY(1NS,-1,9NS),
+    DELAY(2NS,-1,11NS))}
.ENDS 74ACT125


.SUBCKT 74ALS125 A1 C1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 PINDLY(1,1,0) DPWR DGND
+ A1
+ C1
+ Y1
+ IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ TRISTATE:
+ ENABLE LO = C1
+  Y1 = {
+    CASE(
+    TRN_ZH,DELAY(2NS,-1,13NS),
+    TRN_ZL, DELAY(2NS,-1,12NS),
+    TRN_HZ, DELAY(1NS,-1,8NS),
+    TRN_LZ, DELAY(2NS,-1,13NS),
+    TRN_LH, DELAY(3NS,-1,10NS),
+    TRN_HL, DELAY(2NS,-1,10NS),
+    DELAY(4NS,-1,14NS))}
.ENDS 74ALS125


.SUBCKT 74F125 1A 1OEBAR 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1OEBAR 1OE
+     D0_GATE IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 buf3 DPWR DGND
+     1A 1OE 1Y
+     DLY_F125 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_F125 utgate (tplhMN=1.2ns tplhTY=3.6ns tplhMX=6ns 
+		         tphlMN=2.2ns tphlTY=5.1ns tphlMX=7.5ns
+              tplzMN=1ns tplzTY=3.1ns tplzMX=5.5ns
+		         tphzMN=1ns tphzTY=3.1ns tphzMX=5ns
+              tpzlMN=3.2ns tpzlTY=5.6ns tpzlMX=8ns
+		         tpzhMN=2.7ns tpzhTY=5.1ns tpzhMX=7.5ns)
.ENDS 74F125


.SUBCKT 74HC125 1A 1GBAR 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1GBAR 1G
+     D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 buf3 DPWR DGND
+     1A 1G 1Y
+     DLY_HC125 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC125 utgate (tplhTY=14ns tplhMX=24ns tphlTY=14ns tphlMX=24ns
+                               tplzTY=15ns tplzMX=24ns tphzTY=15ns tphzMX=24ns
+                               tpzlTY=14ns tpzlMX=24ns tpzhTY=14ns tpzhMX=24ns)
.ENDS 74HC125


.SUBCKT 74HC125A A1 Y1 OE1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 PINDLY(1,1,0) DPWR DGND
+ A1
+ OE1
+ Y1
+ IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ TRISTATE:
+ ENABLE LO = OE1
+  Y1 = {
+    CASE(
+    TRN_Z$,DELAY(-1,-1,18NS),
+    TRN_$Z, DELAY(-1,-1,24NS),
+    (TRN_LH | TRN_HL), DELAY(-1,-1,18NS),
+    DELAY(-1,-1,25NS))}
.ENDS 74HC125A


.SUBCKT 74HCT125 1A 1Y 1OEBAR
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 PINDLY(1,1,0) DPWR DGND
+ 1A
+ 1OEBAR
+ 1Y
+ IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ TRISTATE:
+ ENABLE LO = 1OEBAR
+  1Y = {
+    CASE(
+    TRN_Z$,DELAY(-1,15NS,28NS),
+    TRN_$Z, DELAY(-1,15NS,25NS),
+    (TRN_LH | TRN_HL), DELAY(-1,15NS,25NS),
+    DELAY(-1,16NS,29NS))}
.ENDS 74HCT125


.SUBCKT 74LS125A 1A 1GBAR 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     1GBAR 1G
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 buf3 DPWR DGND
+     1A 1G 1Y
+     DLY_LS125 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS125 utgate (tplhTY=9ns tplhMX=15ns tphlTY=7ns tphlMX=18ns
+                               tplzMX=20ns tphzMX=20ns
+                               tpzlTY=15ns tpzlMX=25ns tpzhTY=12ns tpzhMX=20ns)
.ENDS 74LS125A


.SUBCKT 74126 1A 1G 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 buf3 DPWR DGND
+     1A 1G 1Y
+     DLY_126 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_126 utgate (tplhTY=8ns tplhMX=13ns tphlTY=12ns tphlMX=18ns
+                               tplzTY=12ns tplzMX=18ns tphzTY=10ns tphzMX=16ns
+                               tpzlTY=16ns tpzlMX=25ns tpzhTY=11ns tpzhMX=18ns)
.ENDS 74126


.SUBCKT 74AC126 A0 B0 O0
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 PINDLY(1,1,0) DPWR DGND
+ B0
+ A0
+ O0
+ IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ TRISTATE:
+ ENABLE HI = A0
+  O0 = {
+    CASE(
+    TRN_ZH,DELAY(1.5NS,-1,8.5NS),
+    TRN_ZL, DELAY(1.5NS,-1,8.5NS),
+    TRN_HZ, DELAY(1.5NS,-1,9.5NS),
+    TRN_LZ, DELAY(1.5NS,-1,9.5NS),
+    TRN_LH, DELAY(1.5NS,-1,6.5NS),
+    TRN_HL, DELAY(1.5NS,-1,6.5NS),
+    DELAY(2.5NS,-1,10.5NS))}
.ENDS 74AC126


.SUBCKT 74ACT126 A0 B0 O0
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 PINDLY(1,1,0) DPWR DGND
+ B0
+ A0
+ O0
+ IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ TRISTATE:
+ ENABLE HI = A0
+  O0 = {
+    CASE(
+    TRN_ZH,DELAY(1.5NS,-1,9NS),
+    TRN_ZL, DELAY(1.5NS,-1,9NS),
+    TRN_HZ, DELAY(1.5NS,-1,10.5NS),
+    TRN_LZ, DELAY(1.5NS,-1,10.5NS),
+    TRN_LH, DELAY(1.5NS,-1,8.5NS),
+    TRN_HL, DELAY(1.5NS,-1,8.5NS),
+    DELAY(2.5NS,-1,11.5NS))}
.ENDS 74ACT126


.SUBCKT 74F126 1A 1OE 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 buf3 DPWR DGND
+     1A 1OE 1Y
+     DLY_F126 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_F126 utgate (tplhMN=2ns tplhTY=4ns tplhMX=6.5ns 
+		         tphlMN=3ns tphlTY=5.5ns tphlMX=8ns
+              tplzMN=3ns tplzTY=5.5ns tplzMX=7.5ns
+		         tphzMN=2ns tphzTY=4.5ns tphzMX=6.5ns
+              tpzlMN=3.8ns tpzlTY=6ns tpzlMX=8ns
+		         tpzhMN=3.8ns tpzhTY=6ns tpzhMX=7.5ns)
.ENDS 74F126


.SUBCKT 74HC126 1A 1G 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 buf3 DPWR DGND
+     1A 1G 1Y
+     DLY_HC126 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC126 utgate (tplhTY=14ns tplhMX=24ns tphlTY=14ns tphlMX=24ns
+                               tplzTY=17ns tplzMX=24ns tphzTY=17ns tphzMX=24ns
+                               tpzlTY=16ns tpzlMX=24ns tpzhTY=16ns tpzhMX=24ns)
.ENDS 74HC126


.SUBCKT 74HC126A A1 Y1 OE1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 PINDLY(1,1,0) DPWR DGND
+ A1
+ OE1
+ Y1
+ IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ TRISTATE:
+ ENABLE HI = OE1
+  Y1 = {
+    CASE(
+    TRN_Z$,DELAY(-1,-1,18NS),
+    TRN_$Z, DELAY(-1,-1,24NS),
+    (TRN_LH | TRN_HL), DELAY(-1,-1,18NS),
+    DELAY(-1,-1,25NS))}
.ENDS 74HC126A


.SUBCKT 74HCT126 1A 1Y 1OE
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 PINDLY(1,1,0) DPWR DGND
+ 1A
+ 1OE
+ 1Y
+ IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ TRISTATE:
+ ENABLE HI = 1OE
+  1Y = {
+    CASE(
+    TRN_Z$,DELAY(-1,13NS,25NS),
+    TRN_$Z, DELAY(-1,18NS,28NS),
+    (TRN_LH | TRN_HL), DELAY(-1,14NS,24NS),
+    DELAY(-1,19NS,29NS))}
.ENDS 74HCT126


.SUBCKT 74LS126A 1A 1G 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 buf3 DPWR DGND
+     1A 1G 1Y
+     DLY_LS126 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS126 utgate (tplhTY=9ns tplhMX=15ns tphlTY=8ns tphlMX=18ns
+                               tplzMX=25ns tphzMX=25ns
+                               tpzlTY=21ns tpzlMX=35ns tpzhTY=16ns tpzhMX=25ns)
.ENDS 74LS126A


.SUBCKT 74128 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nor(2) DPWR DGND
+     1A 1B 1Y
+     DLY_128 IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_128 ugate (tplhTY=6ns tplhMX=9ns tphlTY=8ns tphlMX=12ns)
.ENDS 74128


.SUBCKT 74ALS131 A B C CLK G1 G2BAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(8,8) DPWR DGND
+ G1 G2BAR QA QB QC QABAR QBBAR QCBAR
+ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
+ D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+   ENAB = {G1 & (~G2BAR)}
+   Y0O = {~(QCBAR & QBBAR & QABAR & ENAB)}
+   Y1O = {~(QCBAR & QBBAR & QA & ENAB)}
+   Y2O = {~(QCBAR & QB & QABAR & ENAB)}
+   Y3O = {~(QCBAR & QB & QA & ENAB)}
+   Y4O = {~(QC & QBBAR & QABAR & ENAB)}
+   Y5O = {~(QC & QBBAR & QA & ENAB)}
+   Y6O = {~(QC & QB & QABAR & ENAB)}
+   Y7O = {~(QC & QB & QA & ENAB)}
U2 DFF(3) DPWR DGND
+ $D_HI $D_HI CLK
+ A B C QA QB QC QABAR QBBAR QCBAR
+ D0_EFF IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 PINDLY(8,0,3) DPWR DGND
+ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
+ CLK G1 G2BAR
+ Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+ IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+   ENAB1 = {CHANGED(G1,0)}
+   ENAB2 = {CHANGED(G2BAR,0)}
+   EDGE = {CHANGED_LH(CLK,0)}
+ PINDLY:
+    Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
+     CASE(
+       ENAB1 & TRN_LH, DELAY(7NS,-1,20NS),
+       ENAB1 & TRN_HL, DELAY(6NS,-1,17NS),
+       ENAB2 & (TRN_LH | TRN_HL), DELAY(5NS,-1,15NS),
+       EDGE & TRN_LH, DELAY(8NS,-1,25NS),
+       EDGE & TRN_HL, DELAY(7NS,-1,20NS),
+       DELAY(9NS,-1,26NS))}
U4 CONSTRAINT(4) DPWR DGND
+ CLK A B C
+ IO_ALS00 IO_LEVEL={IO_LEVEL}
+ FREQ:
+  NODE = CLK
+  MAXFREQ = 50MEG
+ WIDTH:
+  NODE = CLK
+  MIN_LO = 10NS
+  MIN_HI = 10NS
+ SETUP_HOLD:
+  CLOCK LH = CLK
+  DATA(3) = A B C
+  SETUPTIME = 10NS
.ENDS 74ALS131


.SUBCKT 74AS131A A B C CLK G1 G2BAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(8,8) DPWR DGND
+ G1 G2BAR QA QB QC QABAR QBBAR QCBAR
+ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
+ D0_GATE IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+   ENAB = {G1 & (~G2BAR)}
+   Y0O = {~(QCBAR & QBBAR & QABAR & ENAB)}
+   Y1O = {~(QCBAR & QBBAR & QA & ENAB)}
+   Y2O = {~(QCBAR & QB & QABAR & ENAB)}
+   Y3O = {~(QCBAR & QB & QA & ENAB)}
+   Y4O = {~(QC & QBBAR & QABAR & ENAB)}
+   Y5O = {~(QC & QBBAR & QA & ENAB)}
+   Y6O = {~(QC & QB & QABAR & ENAB)}
+   Y7O = {~(QC & QB & QA & ENAB)}
U2 DFF(3) DPWR DGND
+ $D_HI $D_HI CLK
+ A B C QA QB QC QABAR QBBAR QCBAR
+ D0_EFF IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 PINDLY(8,0,3) DPWR DGND
+ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
+ CLK G1 G2BAR
+ Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+ IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+   ENAB1 = {CHANGED(G1,0)}
+   ENAB2 = {CHANGED(G2BAR,0)}
+   EDGE = {CHANGED_LH(CLK,0)}
+ PINDLY:
+    Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
+     CASE(
+       ENAB1 & TRN_LH, DELAY(2NS,-1,10NS),
+       ENAB1 & TRN_HL, DELAY(2NS,-1,9NS),
+       ENAB2 & TRN_LH, DELAY(2NS,-1,7NS),
+       ENAB2 & TRN_HL, DELAY(2NS,-1,8.5NS),
+       EDGE & TRN_LH, DELAY(2NS,-1,14.5NS),
+       EDGE & TRN_HL, DELAY(2NS,-1,9.5NS),
+       DELAY(3NS,-1,15.5NS))}
U4 CONSTRAINT(4) DPWR DGND
+ CLK A B C
+ IO_AS00 IO_LEVEL={IO_LEVEL}
+ FREQ:
+  NODE = CLK
+  MAXFREQ = 100MEG
+ WIDTH:
+  NODE = CLK
+  MIN_LO = 5NS
+  MIN_HI = 5NS
+ SETUP_HOLD:
+  CLOCK LH = CLK
+  DATA(3) = A B C
+  SETUPTIME = 3.5NS
.ENDS 74AS131A


.SUBCKT 74132 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_132 IO_STD_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_132 ugate (tplhTY=15ns tplhMX=22ns tphlTY=15ns tphlMX=22ns)
.ENDS 74132


.SUBCKT 74AC132
+ 1A 1B 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ 1A 1B 1Y
+ DLY_AC132 IO_AC_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_AC132 UGATE(TPLHMN=1.8NS TPLHTY=4.2NS TPLHMX=6.9NS
+                TPHLMN=2.3NS TPHLTY=4.8NS TPHLMX=7.3NS)
.ENDS 74AC132


.SUBCKT 74ACT132
+ 1A 1B 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ 1A 1B 1Y
+ DLY_ACT132 IO_ACT_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ACT132 UGATE(TPLHMN=2.6NS TPLHTY=5.3NS TPLHMX=8NS
+                TPHLMN=3.7NS TPHLTY=6.4NS TPHLMX=8.1NS)
.ENDS 74ACT132


.SUBCKT 74ALS132
+ A1 B1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ A1 B1 Y1
+ DLY_ALS132 IO_ALS00_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_ALS132 UGATE(TPLHMN=2NS TPLHMX=12NS
+                       TPHLMN=2NS TPHLMX=11NS)
.ENDS 74ALS132


.SUBCKT 74F132
+ A0 B0 O0BAR
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ A0 B0 O0BAR
+ DLY_F132 IO_F_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_F132 UGATE(TPLHMN=4NS TPLHTY=-1 TPLHMX=10.5NS
+                TPHLMN=5NS TPHLTY=-1 TPHLMX=12.5NS)
.ENDS 74F132


.SUBCKT 74HC132 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_HC132 IO_HC_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC132 ugate (tplhTY=18ns tplhMX=25ns tphlTY=18ns tphlMX=25ns)
.ENDS 74HC132


.SUBCKT 74HC132A
+ A1 B1 Y1
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ A1 B1 Y1
+ DLY_HC132A IO_HC_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HC132A UGATE(TPLHMX=25NS TPHLMX=25NS)
.ENDS 74HC132A


.SUBCKT 74HCT132
+ 1A 1B 1Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(2) DPWR DGND
+ 1A 1B 1Y
+ DLY_HCT132 IO_HCT_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT132 UGATE(TPLHTY=13NS TPLHMX=25NS TPHLTY=13NS TPHLMX=25NS)
.ENDS 74HCT132


.SUBCKT 74LS132 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_LS132 IO_LS_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS132 ugate (tplhTY=15ns tplhMX=22ns tphlTY=15ns tphlMX=22ns)
.ENDS 74LS132


.SUBCKT 74S132 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nand(2) DPWR DGND
+     1A 1B 1Y
+     DLY_S132 IO_S_ST MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S132 ugate (tplhTY=7ns tplhMX=10.5ns tphlTY=8.5ns tphlMX=13ns)
.ENDS 74S132


.SUBCKT 74ALS133 A B C D E F G H I J K L M Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nand(13) DPWR DGND
+     A B C D E F G H I J K L M Y
+     DLY_ALS133 IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_ALS133 ugate (tplhMN=3ns tplhMX=11ns tphlMN=5ns tphlMX=25ns)
.ENDS 74ALS133


.SUBCKT 74F133
+ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 QBAR
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(13) DPWR DGND
+ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 
+ QBAR
+ DLY_F133 IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_F133 UGATE(TPLHMN=2NS TPLHTY=4NS TPLHMX=7NS
+                TPHLMN=2.5NS TPHLTY=4.5NS TPHLMX=7.5NS)
.ENDS 74F133


.SUBCKT 74HC133 A B C D E F G H I J K L M Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nand(13) DPWR DGND
+     A B C D E F G H I J K L M Y
+     DLY_HC133 IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_HC133 ugate (tplhTY=16ns tplhMX=30ns tphlTY=16ns tphlMX=30ns)
.ENDS 74HC133


.SUBCKT 74HCT133
+ A B C D E F G H I J K L M Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(13) DPWR DGND
+ A B C D E F G H I J K L M
+ Y
+ DLY_HCT133 IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_HCT133 UGATE(TPLHMN=-1 TPLHTY=13NS TPLHMX=22NS
+                TPHLMN=-1 TPHLTY=13NS TPHLMX=22NS)
.ENDS 74HCT133


.SUBCKT 74LS133
+ A B C D E F G H I J K L M Y
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 NAND(13) DPWR DGND
+ A B C D E F G H I J K L M
+ Y
+ DLY_LS133 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.MODEL DLY_LS133 UGATE(TPLHMN=-1 TPLHTY=-1 TPLHMX=15NS
+                TPHLMN=-1 TPHLTY=-1 TPHLMX=38NS)
.ENDS 74LS133


.SUBCKT 74S133 A B C D E F G H I J K L M Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nand(13) DPWR DGND
+     A B C D E F G H I J K L M Y
+     DLY_S133 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S133 ugate (tplhTY=4ns tplhMX=6ns tphlTY=4.5ns tphlMX=7ns)
.ENDS 74S133


.SUBCKT 74S134 A B C D E F G H I J K L OCBAR Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 inv DPWR DGND
+     OCBAR OC
+     D0_GATE IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2 nand3(12) DPWR DGND
+     A B C D E F G H I J K L OC Y
+     DLY_S134 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S134 utgate (tplhTY=4ns tplhMX=6ns tphlTY=5ns tphlMX=7.5ns
+                               tplzTY=9ns tplzMX=14ns tphzTY=5.5ns tphzMX=8.5ns
+                               tpzlTY=14ns tpzlMX=21ns tpzhTY=13ns tpzhMX=19.5ns)
.ENDS 74S134


.SUBCKT 74S135 1A 1B C 2A 2B 1Y 2Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xora(4) DPWR DGND
+     1A 1B 1AB C 2A 2B 2AB C
+     1AB 1Y_O 2AB 2Y_O
+     D0_GATE IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(2,0,5) DPWR DGND
+     1Y_O 2Y_O
+     1A 1B C 2A 2B
+     1Y 2Y
+     IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     A1 = {CHANGED(1A,0)}
+     B1 = {CHANGED(1B,0)}
+     A2 = {CHANGED(2A,0)}
+     B2 = {CHANGED(2B,0)}
+     CC = {CHANGED(C,0)}
+     AEQB1 = {1A==1B}
+     ANEQB1 = {1A!=1B}
+     AEQB2 = {2A==2B}
+     ANEQB2 = {2A!=2B}
+
+  PINDLY:
+     1Y = {
+       CASE(
+          A1 & TRN_LH & 1B=='0 & C=='0, DELAY(-1,8.5ns,13ns),
+          B1 & TRN_LH & 1A=='0 & C=='0, DELAY(-1,8.5ns,13ns),
+          A1 & TRN_HL & 1B=='0 & C=='0, DELAY(-1,11ns,15ns),
+          B1 & TRN_HL & 1A=='0 & C=='0, DELAY(-1,11ns,15ns),
+          A1 & TRN_LH & 1B=='1 & C=='0, DELAY(-1,8ns,12ns),
+          B1 & TRN_LH & 1A=='1 & C=='0, DELAY(-1,8ns,12ns),
+          A1 & TRN_HL & 1B=='1 & C=='0, DELAY(-1,9ns,13.5ns),
+          B1 & TRN_HL & 1A=='1 & C=='0, DELAY(-1,9ns,13.5ns),
+          A1 & TRN_LH & 1B=='0 & C=='1, DELAY(-1,10ns,15ns),
+          B1 & TRN_LH & 1A=='0 & C=='1, DELAY(-1,10ns,15ns),
+          A1 & TRN_HL & 1B=='0 & C=='1, DELAY(-1,6.5ns,10ns),
+          B1 & TRN_HL & 1A=='0 & C=='1, DELAY(-1,6.5ns,10ns),
+          A1 & TRN_LH & 1B=='1 & C=='1, DELAY(-1,8.5ns,12ns),
+          B1 & TRN_LH & 1A=='1 & C=='1, DELAY(-1,8.5ns,12ns),
+          A1 & TRN_HL & 1B=='1 & C=='1, DELAY(-1,7ns,13ns),
+          B1 & TRN_HL & 1A=='1 & C=='1, DELAY(-1,7ns,13ns),
+          CC & TRN_LH & AEQB1, DELAY(-1,8ns,12ns),
+          CC & TRN_HL & AEQB1, DELAY(-1,9.5ns,14.5ns),
+          CC & TRN_LH & ANEQB1, DELAY(-1,7.5ns,11.5ns),
+          CC & TRN_HL & ANEQB1, DELAY(-1,8ns,12ns),
+          DELAY(-1,12ns,16ns))}
+
+     2Y = {
+       CASE(
+          A2 & TRN_LH & 2B=='0 & C=='0, DELAY(-1,8.5ns,13ns),
+          B2 & TRN_LH & 2A=='0 & C=='0, DELAY(-1,8.5ns,13ns),
+          A2 & TRN_HL & 2B=='0 & C=='0, DELAY(-1,11ns,15ns),
+          B2 & TRN_HL & 2A=='0 & C=='0, DELAY(-1,11ns,15ns),
+          A2 & TRN_LH & 2B=='1 & C=='0, DELAY(-1,8ns,12ns),
+          B2 & TRN_LH & 2A=='1 & C=='0, DELAY(-1,8ns,12ns),
+          A2 & TRN_HL & 2B=='1 & C=='0, DELAY(-1,9ns,13.5ns),
+          B2 & TRN_HL & 2A=='1 & C=='0, DELAY(-1,9ns,13.5ns),
+          A2 & TRN_LH & 2B=='0 & C=='1, DELAY(-1,10ns,15ns),
+          B2 & TRN_LH & 2A=='0 & C=='1, DELAY(-1,10ns,15ns),
+          A2 & TRN_HL & 2B=='0 & C=='1, DELAY(-1,6.5ns,10ns),
+          B2 & TRN_HL & 2A=='0 & C=='1, DELAY(-1,6.5ns,10ns),
+          A2 & TRN_LH & 2B=='1 & C=='1, DELAY(-1,8.5ns,12ns),
+          B2 & TRN_LH & 2A=='1 & C=='1, DELAY(-1,8.5ns,12ns),
+          A2 & TRN_HL & 2B=='1 & C=='1, DELAY(-1,7ns,13ns),
+          B2 & TRN_HL & 2A=='1 & C=='1, DELAY(-1,7ns,13ns),
+          CC & TRN_LH & AEQB2, DELAY(-1,8ns,12ns),
+          CC & TRN_HL & AEQB2, DELAY(-1,9.5ns,14.5ns),
+          CC & TRN_LH & ANEQB2, DELAY(-1,7.5ns,11.5ns),
+          CC & TRN_HL & ANEQB2, DELAY(-1,8ns,12ns),
+          DELAY(-1,12ns,16ns))}
.ENDS 74S135


.SUBCKT 74136 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR DGND
+     1A 1B 1Y_O
+     D0_GATE IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(1,0,2) DPWR DGND
+     1Y_O
+     1A 1B
+     1Y
+     IO_STD_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     1Y = {
+       CASE(
+          CHANGED(1A,0) & 1B=='0 & TRN_LH, DELAY(-1,12ns,18ns),
+          CHANGED(1B,0) & 1A=='0 & TRN_LH, DELAY(-1,12ns,18ns),
+          CHANGED(1A,0) & 1B=='0 & TRN_HL, DELAY(-1,39ns,50ns),
+          CHANGED(1B,0) & 1A=='0 & TRN_HL, DELAY(-1,39ns,50ns),
+          CHANGED(1A,0) & 1B=='1 & TRN_LH, DELAY(-1,14ns,22ns),
+          CHANGED(1B,0) & 1A=='1 & TRN_LH, DELAY(-1,14ns,22ns),
+          CHANGED(1A,0) & 1B=='1 & TRN_HL, DELAY(-1,42ns,55ns),
+          CHANGED(1B,0) & 1A=='1 & TRN_HL, DELAY(-1,42ns,55ns),
+          DELAY(-1,43ns,56ns))}
.ENDS 74136


.SUBCKT 74ALS136 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR DGND
+     1A 1B 1Y_O
+     D0_GATE IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2DLY PINDLY(1,0,2) DPWR DGND
+     1Y_O
+     1A 1B
+     1Y
+     IO_ALS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     1Y = {
+       CASE(
+          TRN_LH, DELAY(20ns,-1,50ns),
+          CHANGED(1A,0) & 1B=='0 & TRN_HL, DELAY(3ns,-1,15ns),
+          CHANGED(1B,0) & 1A=='0 & TRN_HL, DELAY(3ns,-1,15ns),
+          CHANGED(1A,0) & 1B=='1 & TRN_HL, DELAY(3ns,-1,12ns),
+          CHANGED(1B,0) & 1A=='1 & TRN_HL, DELAY(3ns,-1,12ns),
+          DELAY(21ns,-1,51ns))}
.ENDS 74ALS136


.SUBCKT 74AS136 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR DGND
+     1A 1B 1Y
+     DLY_AS136 IO_AS00_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_AS136 ugate (tplhTY=10.5ns tphlTY=4.3ns)
.ENDS 74AS136


.SUBCKT 74LS136 1A 1B 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 xor DPWR DGND
+     1A 1B 1Y
+     DLY_LS136 IO_LS_OC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_LS136 ugate (tplhTY=18ns tplhMX=30ns tphlTY=18ns tphlMX=30ns)
.ENDS 74LS136


.SUBCKT 74ALS137 GLBAR A B C G1 G2BAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nora(2,6) DPWR DGND
+     ANDA1 NORA2 ANDA2 NORA1 ANDB1 NORB2 ANDB2 NORB1
+     ANDC1 NORC2 ANDC2 NORC1
+     NORA1 NORA2 NORB1 NORB2 NORC1 NORC2
+     D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2LOG LOGICEXP(12,14) DPWR DGND
+     GLBAR A B C G1 G2BAR NORA1 NORA2 NORB1 NORB2 NORC1 NORC2
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O ANDA1 ANDA2 ANDB1 ANDB2
+     ANDC1 ANDC2
+     D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     gl = {~GLBAR}
+     enout = {~(G2BAR | (~G1))}
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     ANDA1 = {abar & gl}
+     ANDA2 = {A & gl}
+     ANDB1 = {bbar & gl}
+     ANDB2 = {B & gl}
+     ANDC1 = {cbar & gl}
+     ANDC2 = {C & gl}
+     Y0_O = {~(NORA2 & NORB2 & NORC2 & enout)}
+     Y1_O = {~(NORA1 & NORB2 & NORC2 & enout)}
+     Y2_O = {~(NORA2 & NORB1 & NORC2 & enout)}
+     Y3_O = {~(NORA1 & NORB1 & NORC2 & enout)}
+     Y4_O = {~(NORA2 & NORB2 & NORC1 & enout)}
+     Y5_O = {~(NORA1 & NORB2 & NORC1 & enout)}
+     Y6_O = {~(NORA2 & NORB1 & NORC1 & enout)}
+     Y7_O = {~(NORA1 & NORB1 & NORC1 & enout)}
U3DLY PINDLY(8,0,6) DPWR DGND
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     GLBAR A B C G1 G2BAR
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
+     GLEN = {CHANGED(GLBAR,0)}
+     G1EN = {CHANGED(G1,0)}
+     G2EN = {CHANGED(G2BAR,0)}
+
+  PINDLY:
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
+        CASE(
+          GLEN & TRN_LH, DELAY(7ns,-1,22ns),
+          GLEN & TRN_HL, DELAY(7ns,-1,20ns),
+          IN & TRN_LH, DELAY(5ns,-1,20ns),
+          IN & TRN_HL, DELAY(6ns,-1,20ns),
+          G1EN & TRN_LH, DELAY(5ns,-1,17ns),
+          G1EN & TRN_HL, DELAY(5ns,-1,15ns),
+          G2EN & TRN_LH, DELAY(4ns,-1,12ns),
+          G2EN & TRN_HL, DELAY(5ns,-1,15ns),
+          DELAY(8ns,-1,23ns))}
U4CON CONSTRAINT(4) DPWR DGND
+     GLBAR A B C
+     IO_ALS00 IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=GLBAR
+     MIN_LO=10ns
+
+  SETUP_HOLD:
+     CLOCK LH=GLBAR
+     DATA(3)=A B C
+     SETUPTIME=10ns
+     HOLDTIME=5ns
.ENDS 74ALS137


.SUBCKT 74AS137 GLBAR A B C G1 G2BAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nora(2,6) DPWR DGND
+     ANDA1 NORA2 ANDA2 NORA1 ANDB1 NORB2 ANDB2 NORB1
+     ANDC1 NORC2 ANDC2 NORC1
+     NORA1 NORA2 NORB1 NORB2 NORC1 NORC2
+     D0_GATE IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2LOG LOGICEXP(12,14) DPWR DGND
+     GLBAR A B C G1 G2BAR NORA1 NORA2 NORB1 NORB2 NORC1 NORC2
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O ANDA1 ANDA2 ANDB1 ANDB2
+     ANDC1 ANDC2
+     D0_GATE IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     gl = {~GLBAR}
+     enout = {~(G2BAR | (~G1))}
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     ANDA1 = {abar & gl}
+     ANDA2 = {A & gl}
+     ANDB1 = {bbar & gl}
+     ANDB2 = {B & gl}
+     ANDC1 = {cbar & gl}
+     ANDC2 = {C & gl}
+     Y0_O = {~(NORA2 & NORB2 & NORC2 & enout)}
+     Y1_O = {~(NORA1 & NORB2 & NORC2 & enout)}
+     Y2_O = {~(NORA2 & NORB1 & NORC2 & enout)}
+     Y3_O = {~(NORA1 & NORB1 & NORC2 & enout)}
+     Y4_O = {~(NORA2 & NORB2 & NORC1 & enout)}
+     Y5_O = {~(NORA1 & NORB2 & NORC1 & enout)}
+     Y6_O = {~(NORA2 & NORB1 & NORC1 & enout)}
+     Y7_O = {~(NORA1 & NORB1 & NORC1 & enout)}
U3DLY PINDLY(8,0,6) DPWR DGND
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     GLBAR A B C G1 G2BAR
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
+     GLEN = {CHANGED(GLBAR,0)}
+     G1EN = {CHANGED(G1,0)}
+     G2EN = {CHANGED(G2BAR,0)}
+
+  PINDLY:
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
+        CASE(
+          GLEN & TRN_LH, DELAY(3ns,-1,13.5ns),
+          GLEN & TRN_HL, DELAY(3ns,-1,14ns),
+          IN & TRN_LH, DELAY(2ns,-1,12.5ns),
+          IN & TRN_HL, DELAY(2ns,-1,12.5ns),
+          G1EN & TRN_LH, DELAY(2ns,-1,10ns),
+          G1EN & TRN_HL, DELAY(2ns,-1,9ns),
+          G2EN & TRN_LH, DELAY(2ns,-1,8ns),
+          G2EN & TRN_HL, DELAY(2ns,-1,8.5ns),
+          DELAY(4ns,-1,15ns))}
U4CON CONSTRAINT(4) DPWR DGND
+     GLBAR A B C
+     IO_AS00 IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=GLBAR
+     MIN_LO=4.5ns
+
+  SETUP_HOLD:
+     CLOCK LH=GLBAR
+     DATA(3)=A B C
+     SETUPTIME=4ns
+     HOLDTIME=1ns
.ENDS 74AS137


.SUBCKT 74HC137 GLBAR A B C G1 G2BAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nora(2,6) DPWR DGND
+     ANDA1 NORA2 ANDA2 NORA1 ANDB1 NORB2 ANDB2 NORB1
+     ANDC1 NORC2 ANDC2 NORC1
+     NORA1 NORA2 NORB1 NORB2 NORC1 NORC2
+     D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2LOG LOGICEXP(12,14) DPWR DGND
+     GLBAR A B C G1 G2BAR NORA1 NORA2 NORB1 NORB2 NORC1 NORC2
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O ANDA1 ANDA2 ANDB1 ANDB2
+     ANDC1 ANDC2
+     D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     gl = {~GLBAR}
+     enout = {~(G2BAR | (~G1))}
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     ANDA1 = {abar & gl}
+     ANDA2 = {A & gl}
+     ANDB1 = {bbar & gl}
+     ANDB2 = {B & gl}
+     ANDC1 = {cbar & gl}
+     ANDC2 = {C & gl}
+     Y0_O = {~(NORA2 & NORB2 & NORC2 & enout)}
+     Y1_O = {~(NORA1 & NORB2 & NORC2 & enout)}
+     Y2_O = {~(NORA2 & NORB1 & NORC2 & enout)}
+     Y3_O = {~(NORA1 & NORB1 & NORC2 & enout)}
+     Y4_O = {~(NORA2 & NORB2 & NORC1 & enout)}
+     Y5_O = {~(NORA1 & NORB2 & NORC1 & enout)}
+     Y6_O = {~(NORA2 & NORB1 & NORC1 & enout)}
+     Y7_O = {~(NORA1 & NORB1 & NORC1 & enout)}
U3DLY PINDLY(8,0,6) DPWR DGND
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     GLBAR A B C G1 G2BAR
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
+     GLEN = {CHANGED(GLBAR,0)}
+     G1EN = {CHANGED(G1,0)}
+     G2EN = {CHANGED(G2BAR,0)}
+
+  PINDLY:
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
+        CASE(
+          GLEN, DELAY(-1,22ns,38ns),
+          IN, DELAY(-1,23ns,38ns),
+          G1EN, DELAY(-1,17ns,29ns),
+          G2EN, DELAY(-1,17ns,29ns),
+          DELAY(-1,24ns,39ns))}
U4CON CONSTRAINT(4) DPWR DGND
+     GLBAR A B C
+     IO_HC IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=GLBAR
+     MIN_LO=20ns
+
+  SETUP_HOLD:
+     CLOCK LH=GLBAR
+     DATA(3)=A B C
+     SETUPTIME=19ns
+     HOLDTIME=5ns
.ENDS 74HC137


.SUBCKT 74HCT137 GLBAR A B C G1 G2BAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nora(2,6) DPWR DGND
+     ANDA1 NORA2 ANDA2 NORA1 ANDB1 NORB2 ANDB2 NORB1
+     ANDC1 NORC2 ANDC2 NORC1
+     NORA1 NORA2 NORB1 NORB2 NORC1 NORC2
+     D0_GATE IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2LOG LOGICEXP(12,14) DPWR DGND
+     GLBAR A B C G1 G2BAR NORA1 NORA2 NORB1 NORB2 NORC1 NORC2
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O ANDA1 ANDA2 ANDB1 ANDB2
+     ANDC1 ANDC2
+     D0_GATE IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     gl = {~GLBAR}
+     enout = {~(G2BAR | (~G1))}
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     ANDA1 = {abar & gl}
+     ANDA2 = {A & gl}
+     ANDB1 = {bbar & gl}
+     ANDB2 = {B & gl}
+     ANDC1 = {cbar & gl}
+     ANDC2 = {C & gl}
+     Y0_O = {~(NORA2 & NORB2 & NORC2 & enout)}
+     Y1_O = {~(NORA1 & NORB2 & NORC2 & enout)}
+     Y2_O = {~(NORA2 & NORB1 & NORC2 & enout)}
+     Y3_O = {~(NORA1 & NORB1 & NORC2 & enout)}
+     Y4_O = {~(NORA2 & NORB2 & NORC1 & enout)}
+     Y5_O = {~(NORA1 & NORB2 & NORC1 & enout)}
+     Y6_O = {~(NORA2 & NORB1 & NORC1 & enout)}
+     Y7_O = {~(NORA1 & NORB1 & NORC1 & enout)}
U3DLY PINDLY(8,0,6) DPWR DGND
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     GLBAR A B C G1 G2BAR
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
+     GLEN = {CHANGED(GLBAR,0)}
+     G1EN = {CHANGED(G1,0)}
+     G2EN = {CHANGED(G2BAR,0)}
+
+  PINDLY:
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
+        CASE(
+          GLEN, DELAY(-1,32ns,42ns),
+          IN, DELAY(-1,25ns,38ns),
+          G1EN, DELAY(-1,20ns,29ns),
+          G2EN, DELAY(-1,20ns,29ns),
+          DELAY(-1,33ns,43ns))}
U4CON CONSTRAINT(4) DPWR DGND
+     GLBAR A B C
+     IO_HCT IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=GLBAR
+     MIN_LO=33ns
+
+  SETUP_HOLD:
+     CLOCK LH=GLBAR
+     DATA(3)=A B C
+     SETUPTIME=19ns
+     HOLDTIME=5ns
.ENDS 74HCT137


.SUBCKT 74LS137 GLBAR A B C G1 G2BAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nora(2,6) DPWR DGND
+     ANDA1 NORA2 ANDA2 NORA1 ANDB1 NORB2 ANDB2 NORB1
+     ANDC1 NORC2 ANDC2 NORC1
+     NORA1 NORA2 NORB1 NORB2 NORC1 NORC2
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U2LOG LOGICEXP(12,14) DPWR DGND
+     GLBAR A B C G1 G2BAR NORA1 NORA2 NORB1 NORB2 NORC1 NORC2
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O ANDA1 ANDA2 ANDB1 ANDB2
+     ANDC1 ANDC2
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     gl = {~GLBAR}
+     enout = {~(G2BAR | (~G1))}
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     ANDA1 = {abar & gl}
+     ANDA2 = {A & gl}
+     ANDB1 = {bbar & gl}
+     ANDB2 = {B & gl}
+     ANDC1 = {cbar & gl}
+     ANDC2 = {C & gl}
+     Y0_O = {~(NORA2 & NORB2 & NORC2 & enout)}
+     Y1_O = {~(NORA1 & NORB2 & NORC2 & enout)}
+     Y2_O = {~(NORA2 & NORB1 & NORC2 & enout)}
+     Y3_O = {~(NORA1 & NORB1 & NORC2 & enout)}
+     Y4_O = {~(NORA2 & NORB2 & NORC1 & enout)}
+     Y5_O = {~(NORA1 & NORB2 & NORC1 & enout)}
+     Y6_O = {~(NORA2 & NORB1 & NORC1 & enout)}
+     Y7_O = {~(NORA1 & NORB1 & NORC1 & enout)}
U3DLY PINDLY(8,0,6) DPWR DGND
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     GLBAR A B C G1 G2BAR
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
+     INA = {CHANGED(A,0)}
+     INB = {CHANGED(B,0)}
+     INC = {CHANGED(C,0)}
+     GLEN = {CHANGED(GLBAR,0)}
+     G1EN = {CHANGED(G1,0)}
+     G2EN = {CHANGED(G2BAR,0)}
+
+  PINDLY:
+     Y0 = {
+        CASE(
+          GLEN & TRN_LH, DELAY(-1,18ns,27ns),
+          GLEN & TRN_HL, DELAY(-1,25ns,38ns),
+          IN & TRN_LH, DELAY(-1,16ns,24ns),
+          IN & TRN_HL, DELAY(-1,19ns,29ns),
+          G1EN & TRN_LH, DELAY(-1,14ns,21ns),
+          G1EN & TRN_HL, DELAY(-1,18ns,27ns),
+          G2EN & TRN_LH, DELAY(-1,13ns,21ns),
+          G2EN & TRN_HL, DELAY(-1,16ns,27ns),
+          DELAY(-1,26ns,39ns))}
+     Y1 = {
+        CASE(
+          GLEN & TRN_LH, DELAY(-1,18ns,27ns),
+          GLEN & TRN_HL, DELAY(-1,25ns,38ns),
+          INA & TRN_HL, DELAY(-1,25ns,38ns),
+          IN & TRN_LH, DELAY(-1,16ns,24ns),
+          (INB | INC) & TRN_HL, DELAY(-1,19ns,29ns),
+          G1EN & TRN_LH, DELAY(-1,14ns,21ns),
+          G1EN & TRN_HL, DELAY(-1,18ns,27ns),
+          G2EN & TRN_LH, DELAY(-1,13ns,21ns),
+          G2EN & TRN_HL, DELAY(-1,16ns,27ns),
+          DELAY(-1,26ns,39ns))}
+     Y2 = {
+        CASE(
+          GLEN & TRN_LH, DELAY(-1,18ns,27ns),
+          GLEN & TRN_HL, DELAY(-1,25ns,38ns),
+          INB & TRN_HL, DELAY(-1,25ns,38ns),
+          IN & TRN_LH, DELAY(-1,16ns,24ns),
+          (INA | INC) & TRN_HL, DELAY(-1,19ns,29ns),
+          G1EN & TRN_LH, DELAY(-1,14ns,21ns),
+          G1EN & TRN_HL, DELAY(-1,18ns,27ns),
+          G2EN & TRN_LH, DELAY(-1,13ns,21ns),
+          G2EN & TRN_HL, DELAY(-1,16ns,27ns),
+          DELAY(-1,26ns,39ns))}
+     Y3 = {
+        CASE(
+          GLEN & TRN_LH, DELAY(-1,18ns,27ns),
+          GLEN & TRN_HL, DELAY(-1,25ns,38ns),
+          (INA | INB) & TRN_HL, DELAY(-1,25ns,38ns),
+          IN & TRN_LH, DELAY(-1,16ns,24ns),
+          INC & TRN_HL, DELAY(-1,19ns,29ns),
+          G1EN & TRN_LH, DELAY(-1,14ns,21ns),
+          G1EN & TRN_HL, DELAY(-1,18ns,27ns),
+          G2EN & TRN_LH, DELAY(-1,13ns,21ns),
+          G2EN & TRN_HL, DELAY(-1,16ns,27ns),
+          DELAY(-1,26ns,39ns))}
+     Y4 = {
+        CASE(
+          GLEN & TRN_LH, DELAY(-1,18ns,27ns),
+          GLEN & TRN_HL, DELAY(-1,25ns,38ns),
+          INC & TRN_HL, DELAY(-1,25ns,38ns),
+          IN & TRN_LH, DELAY(-1,16ns,24ns),
+          (INA | INB) & TRN_HL, DELAY(-1,19ns,29ns),
+          G1EN & TRN_LH, DELAY(-1,14ns,21ns),
+          G1EN & TRN_HL, DELAY(-1,18ns,27ns),
+          G2EN & TRN_LH, DELAY(-1,13ns,21ns),
+          G2EN & TRN_HL, DELAY(-1,16ns,27ns),
+          DELAY(-1,26ns,39ns))}
+     Y5 = {
+        CASE(
+          GLEN & TRN_LH, DELAY(-1,18ns,27ns),
+          GLEN & TRN_HL, DELAY(-1,25ns,38ns),
+          (INA | INC) & TRN_HL, DELAY(-1,25ns,38ns),
+          IN & TRN_LH, DELAY(-1,16ns,24ns),
+          INB & TRN_HL, DELAY(-1,19ns,29ns),
+          G1EN & TRN_LH, DELAY(-1,14ns,21ns),
+          G1EN & TRN_HL, DELAY(-1,18ns,27ns),
+          G2EN & TRN_LH, DELAY(-1,13ns,21ns),
+          G2EN & TRN_HL, DELAY(-1,16ns,27ns),
+          DELAY(-1,26ns,39ns))}
+     Y6 = {
+        CASE(
+          GLEN & TRN_LH, DELAY(-1,18ns,27ns),
+          GLEN & TRN_HL, DELAY(-1,25ns,38ns),
+          (INB | INC) & TRN_HL, DELAY(-1,25ns,38ns),
+          IN & TRN_LH, DELAY(-1,16ns,24ns),
+          INA & TRN_HL, DELAY(-1,19ns,29ns),
+          G1EN & TRN_LH, DELAY(-1,14ns,21ns),
+          G1EN & TRN_HL, DELAY(-1,18ns,27ns),
+          G2EN & TRN_LH, DELAY(-1,13ns,21ns),
+          G2EN & TRN_HL, DELAY(-1,16ns,27ns),
+          DELAY(-1,26ns,39ns))}
+     Y7 = {
+        CASE(
+          GLEN & TRN_LH, DELAY(-1,18ns,27ns),
+          GLEN & TRN_HL, DELAY(-1,25ns,38ns),
+          IN & TRN_LH, DELAY(-1,16ns,24ns),
+          IN & TRN_HL, DELAY(-1,25ns,38ns),
+          G1EN & TRN_LH, DELAY(-1,14ns,21ns),
+          G1EN & TRN_HL, DELAY(-1,18ns,27ns),
+          G2EN & TRN_LH, DELAY(-1,13ns,21ns),
+          G2EN & TRN_HL, DELAY(-1,16ns,27ns),
+          DELAY(-1,26ns,39ns))}
U4CON CONSTRAINT(4) DPWR DGND
+     GLBAR A B C
+     IO_LS IO_LEVEL={IO_LEVEL}
+
+  WIDTH:
+     NODE=GLBAR
+     MIN_LO=15ns
+
+  SETUP_HOLD:
+     CLOCK LH=GLBAR
+     DATA(3)=A B C
+     SETUPTIME=10ns
+     HOLDTIME=10ns
.ENDS 74LS137


.SUBCKT 74AC138 A0 A1 A2 E1BAR E2BAR E3 O0 O1 O2 O3 O4 O5 O6 O7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(6,8) DPWR DGND
+     A0 A1 A2 E1BAR E2BAR E3
+     O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O
+     D0_GATE IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     a0bar = {~A0}
+     a1bar = {~A1}
+     a2bar = {~A2}
+     enable = {(~E1BAR) & (~E2BAR) & E3}
+     O0_O = {~(a0bar & a1bar & a2bar & enable)}
+     O1_O = {~(A0 & a1bar & a2bar & enable)}
+     O2_O = {~(a0bar & A1 & a2bar & enable)}
+     O3_O = {~(A0 & A1 & a2bar & enable)}
+     O4_O = {~(a0bar & a1bar & A2 & enable)}
+     O5_O = {~(A0 & a1bar & A2 & enable)}
+     O6_O = {~(a0bar & A1 & A2 & enable)}
+     O7_O = {~(A0 & A1 & A2 & enable)}
U2DLY PINDLY(8,0,6) DPWR DGND
+     O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O
+     A0 A1 A2 E1BAR E2BAR E3
+     O0 O1 O2 O3 O4 O5 O6 O7
+     IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0)}
+     ENBAR = {CHANGED(E1BAR,0) | CHANGED(E2BAR,0)}
+     EN = {CHANGED(E3,0)}
+
+  PINDLY:
+     O0 O1 O2 O3 O4 O5 O6 O7 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(1.5ns,8ns,11ns),
+          ENBAR & TRN_HL, DELAY(1.5ns,7ns,9.5ns),
+          EN & TRN_LH, DELAY(1.5ns,8ns,11ns),
+          EN & TRN_HL, DELAY(1.5ns,6ns,8ns),
+          IN & TRN_LH, DELAY(1.5ns,6.5ns,9.5ns),
+          IN & TRN_HL, DELAY(1.5ns,6ns,9ns),
+          DELAY(2.5ns,9ns,12ns))}
.ENDS 74AC138


.SUBCKT 74ACT138 A0 A1 A2 E1BAR E2BAR E3 O0 O1 O2 O3 O4 O5 O6 O7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(6,8) DPWR DGND
+     A0 A1 A2 E1BAR E2BAR E3
+     O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O
+     D0_GATE IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     a0bar = {~A0}
+     a1bar = {~A1}
+     a2bar = {~A2}
+     enable = {(~E1BAR) & (~E2BAR) & E3}
+     O0_O = {~(a0bar & a1bar & a2bar & enable)}
+     O1_O = {~(A0 & a1bar & a2bar & enable)}
+     O2_O = {~(a0bar & A1 & a2bar & enable)}
+     O3_O = {~(A0 & A1 & a2bar & enable)}
+     O4_O = {~(a0bar & a1bar & A2 & enable)}
+     O5_O = {~(A0 & a1bar & A2 & enable)}
+     O6_O = {~(a0bar & A1 & A2 & enable)}
+     O7_O = {~(A0 & A1 & A2 & enable)}
U2DLY PINDLY(8,0,6) DPWR DGND
+     O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O
+     A0 A1 A2 E1BAR E2BAR E3
+     O0 O1 O2 O3 O4 O5 O6 O7
+     IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0)}
+     ENBAR = {CHANGED(E1BAR,0) | CHANGED(E2BAR,0)}
+     EN = {CHANGED(E3,0)}
+
+  PINDLY:
+     O0 O1 O2 O3 O4 O5 O6 O7 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(2.5ns,8ns,11.5ns),
+          ENBAR & TRN_HL, DELAY(2ns,7.5ns,11.5ns),
+          EN & TRN_LH, DELAY(2.5ns,8ns,12ns),
+          EN & TRN_HL, DELAY(2ns,6.5ns,10.5ns),
+          IN & TRN_LH, DELAY(1.5ns,7ns,10.5ns),
+          IN & TRN_HL, DELAY(1.5ns,6.5ns,10.5ns),
+          DELAY(3.5ns,9ns,13ns))}
.ENDS 74ACT138


.SUBCKT 74ALS138 A B C G1 G2ABAR G2BBAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(6,8) DPWR DGND
+     A B C G1 G2ABAR G2BBAR
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     enable = {(~G2ABAR) & (~G2BBAR) & G1}
+     Y0_O = {~(abar & bbar & cbar & enable)}
+     Y1_O = {~(A & bbar & cbar & enable)}
+     Y2_O = {~(abar & B & cbar & enable)}
+     Y3_O = {~(A & B & cbar & enable)}
+     Y4_O = {~(abar & bbar & C & enable)}
+     Y5_O = {~(A & bbar & C & enable)}
+     Y6_O = {~(abar & B & C & enable)}
+     Y7_O = {~(A & B & C & enable)}
U2DLY PINDLY(8,0,6) DPWR DGND
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     A B C G1 G2ABAR G2BBAR
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
+     EN = {CHANGED(G2ABAR,0) | CHANGED(G2BBAR,0) | CHANGED(G1,0)}
+
+  PINDLY:
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
+       CASE(
+          IN & TRN_LH, DELAY(6ns,-1,22ns),
+          IN & TRN_HL, DELAY(6ns,-1,18ns),
+          EN & TRN_LH, DELAY(4ns,-1,17ns),
+          EN & TRN_HL, DELAY(5ns,-1,17ns),
+          DELAY(7ns,-1,23ns))}
.ENDS 74ALS138


.SUBCKT 74AS138 A B C G1 G2ABAR G2BBAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(6,8) DPWR DGND
+     A B C G1 G2ABAR G2BBAR
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     D0_GATE IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     enable = {(~G2ABAR) & (~G2BBAR) & G1}
+     Y0_O = {~(abar & bbar & cbar & enable)}
+     Y1_O = {~(A & bbar & cbar & enable)}
+     Y2_O = {~(abar & B & cbar & enable)}
+     Y3_O = {~(A & B & cbar & enable)}
+     Y4_O = {~(abar & bbar & C & enable)}
+     Y5_O = {~(A & bbar & C & enable)}
+     Y6_O = {~(abar & B & C & enable)}
+     Y7_O = {~(A & B & C & enable)}
U2DLY PINDLY(8,0,6) DPWR DGND
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     A B C G1 G2ABAR G2BBAR
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
+     ENBAR = {CHANGED(G2ABAR,0) | CHANGED(G2BBAR,0)}
+     EN = {CHANGED(G1,0)}
+
+  PINDLY:
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
+       CASE(
+          EN & TRN_LH, DELAY(2ns,-1,10ns),
+          EN & TRN_HL, DELAY(2ns,-1,10ns),
+          IN & TRN_LH, DELAY(2ns,-1,10ns),
+          IN & TRN_HL, DELAY(2ns,-1,9.5ns),
+          ENBAR & TRN_LH, DELAY(2ns,-1,7.5ns),
+          ENBAR & TRN_HL, DELAY(2ns,-1,8.5ns),
+          DELAY(3ns,-1,11ns))}
.ENDS 74AS138


.SUBCKT 74F138 A0 A1 A2 E0BAR E1BAR E2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(6,8) DPWR DGND
+     A0 A1 A2 E0BAR E1BAR E2
+     Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O
+     D0_GATE IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     a0bar = {~A0}
+     a1bar = {~A1}
+     a2bar = {~A2}
+     enable = {(~E0BAR) & (~E1BAR) & E2}
+     Q0_O = {~(a0bar & a1bar & a2bar & enable)}
+     Q1_O = {~(A0 & a1bar & a2bar & enable)}
+     Q2_O = {~(a0bar & A1 & a2bar & enable)}
+     Q3_O = {~(A0 & A1 & a2bar & enable)}
+     Q4_O = {~(a0bar & a1bar & A2 & enable)}
+     Q5_O = {~(A0 & a1bar & A2 & enable)}
+     Q6_O = {~(a0bar & A1 & A2 & enable)}
+     Q7_O = {~(A0 & A1 & A2 & enable)}
U2DLY PINDLY(8,0,6) DPWR DGND
+     Q0_O Q1_O Q2_O Q3_O Q4_O Q5_O Q6_O Q7_O
+     A0 A1 A2 E0BAR E1BAR E2
+     Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
+     IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0)}
+     ENBAR = {CHANGED(E0BAR,0) | CHANGED(E1BAR,0)}
+     EN = {CHANGED(E2,0)}
+
+  PINDLY:
+     Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(3.5ns,6.4ns,7ns),
+          EN & TRN_HL, DELAY(3.5ns,5.6ns,7.5ns),
+          ENBAR & TRN_HL, DELAY(3ns,5.3ns,7ns),
+          EN & TRN_LH, DELAY(4ns,6.2ns,8ns),
+          IN & TRN_LH, DELAY(3.5ns,5.6ns,7ns),
+          IN & TRN_HL, DELAY(4ns,6.1ns,8ns),
+          DELAY(5ns,7.4ns,9ns))}
.ENDS 74F138


.SUBCKT 74HC138 A B C G1 G2ABAR G2BBAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(6,8) DPWR DGND
+     A B C G1 G2ABAR G2BBAR
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     enable = {(~G2ABAR) & (~G2BBAR) & G1}
+     Y0_O = {~(abar & bbar & cbar & enable)}
+     Y1_O = {~(A & bbar & cbar & enable)}
+     Y2_O = {~(abar & B & cbar & enable)}
+     Y3_O = {~(A & B & cbar & enable)}
+     Y4_O = {~(abar & bbar & C & enable)}
+     Y5_O = {~(A & bbar & C & enable)}
+     Y6_O = {~(abar & B & C & enable)}
+     Y7_O = {~(A & B & C & enable)}
U2DLY PINDLY(8,0,6) DPWR DGND
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     A B C G1 G2ABAR G2BBAR
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
+     EN = {CHANGED(G2ABAR,0) | CHANGED(G2BBAR,0) | CHANGED(G1,0)}
+
+  PINDLY:
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
+       CASE(
+          EN, DELAY(-1,18ns,31ns),
+          IN, DELAY(-1,18ns,36ns),
+          DELAY(-1,19ns,37ns))}
.ENDS 74HC138


.SUBCKT 74HC138A A0 A1 A2 CS1 CS2 CS3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(6,8) DPWR DGND
+ A0 A1 A2 CS1 CS2 CS3
+ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
+ D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+   ENAB = {CS1 & ~CS2 & ~CS3}
+   Y0O = {~(~A0 & ~A1 & ~A2 & ENAB)}
+   Y1O = {~(A0 & ~A1 & ~A2 & ENAB)}
+   Y2O = {~(~A0 & A1 & ~A2 & ENAB)}
+   Y3O = {~(A0 & A1 & ~A2 & ENAB)}
+   Y4O = {~(~A0 & ~A1 & A2 & ENAB)}
+   Y5O = {~(A0 & ~A1 & A2 & ENAB)}
+   Y6O = {~(~A0 & A1 & A2 & ENAB)}
+   Y7O = {~(A0 & A1 & A2 & ENAB)}
U2 PINDLY(8,0,6) DPWR DGND
+ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
+ A0 A1 A2 CS1 CS2 CS3
+ Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+ IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+     IN = {CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0)}
+     ENBAR = {CHANGED(CS2,0) | CHANGED(CS3,0)}
+     EN = {CHANGED(CS1,0)}
+  PINDLY:
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
+       CASE(
+          EN & TRN_LH, DELAY(-1,-1,22NS),
+          EN & TRN_HL, DELAY(-1,-1,22NS),
+          ENBAR & TRN_LH, DELAY(-1,-1,24NS),
+          ENBAR & TRN_HL, DELAY(-1,-1,24NS),
+          IN & TRN_LH, DELAY(-1,-1,27NS),
+          IN & TRN_HL, DELAY(-1,-1,27NS),
+          DELAY(-1,-1,28NS))}
.ENDS 74HC138A


.SUBCKT 74HCT138 A B C G1 G2ABAR G2BBAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(6,8) DPWR DGND
+     A B C G1 G2ABAR G2BBAR
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     D0_GATE IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     enable = {(~G2ABAR) & (~G2BBAR) & G1}
+     Y0_O = {~(abar & bbar & cbar & enable)}
+     Y1_O = {~(A & bbar & cbar & enable)}
+     Y2_O = {~(abar & B & cbar & enable)}
+     Y3_O = {~(A & B & cbar & enable)}
+     Y4_O = {~(abar & bbar & C & enable)}
+     Y5_O = {~(A & bbar & C & enable)}
+     Y6_O = {~(abar & B & C & enable)}
+     Y7_O = {~(A & B & C & enable)}
U2DLY PINDLY(8,0,6) DPWR DGND
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     A B C G1 G2ABAR G2BBAR
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
+     EN = {CHANGED(G2ABAR,0) | CHANGED(G2BBAR,0) | CHANGED(G1,0)}
+
+  PINDLY:
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
+       CASE(
+          EN, DELAY(-1,22ns,33ns),
+          IN, DELAY(-1,23ns,36ns),
+          DELAY(-1,24ns,37ns))}
.ENDS 74HCT138


.SUBCKT 74HCT138A A0 A1 A2 CS1 CS2 CS3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(6,8) DPWR DGND
+ A0 A1 A2 CS1 CS2 CS3
+ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
+ D0_GATE IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+   ENAB = {CS1 & ~CS2 & ~CS3}
+   Y0O = {~(~A0 & ~A1 & ~A2 & ENAB)}
+   Y1O = {~(A0 & ~A1 & ~A2 & ENAB)}
+   Y2O = {~(~A0 & A1 & ~A2 & ENAB)}
+   Y3O = {~(A0 & A1 & ~A2 & ENAB)}
+   Y4O = {~(~A0 & ~A1 & A2 & ENAB)}
+   Y5O = {~(A0 & ~A1 & A2 & ENAB)}
+   Y6O = {~(~A0 & A1 & A2 & ENAB)}
+   Y7O = {~(A0 & A1 & A2 & ENAB)}
U2 PINDLY(8,0,6) DPWR DGND
+ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
+ A0 A1 A2 CS1 CS2 CS3
+ Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+ IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+     IN = {CHANGED(A0,0) | CHANGED(A1,0) | CHANGED(A2,0)}
+     ENBAR = {CHANGED(CS2,0) | CHANGED(CS3,0)}
+     EN = {CHANGED(CS1,0)}
+  PINDLY:
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 = {
+       CASE(
+          EN & TRN_LH, DELAY(-1,-1,27NS),
+          EN & TRN_HL, DELAY(-1,-1,27NS),
+          ENBAR & TRN_LH, DELAY(-1,-1,30NS),
+          ENBAR & TRN_HL, DELAY(-1,-1,30NS),
+          IN & TRN_LH, DELAY(-1,-1,30NS),
+          IN & TRN_HL, DELAY(-1,-1,30NS),
+          DELAY(-1,-1,31NS))}
.ENDS 74HCT138A


.SUBCKT 74LS138 A B C G1 G2ABAR G2BBAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(6,8) DPWR DGND
+     A B C G1 G2ABAR G2BBAR
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     enable = {(~G2ABAR) & (~G2BBAR) & G1}
+     Y0_O = {~(abar & bbar & cbar & enable)}
+     Y1_O = {~(A & bbar & cbar & enable)}
+     Y2_O = {~(abar & B & cbar & enable)}
+     Y3_O = {~(A & B & cbar & enable)}
+     Y4_O = {~(abar & bbar & C & enable)}
+     Y5_O = {~(A & bbar & C & enable)}
+     Y6_O = {~(abar & B & C & enable)}
+     Y7_O = {~(A & B & C & enable)}
U2DLY PINDLY(8,0,6) DPWR DGND
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     A B C G1 G2ABAR G2BBAR
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
+     INA = {CHANGED(A,0)}
+     INB = {CHANGED(B,0)}
+     INC = {CHANGED(C,0)}
+     ENBAR = {CHANGED(G2ABAR,0) | CHANGED(G2BBAR,0)}
+     EN = {CHANGED(G1,0)}
+
+  PINDLY:
+     Y0 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,12ns,18ns),
+          ENBAR & TRN_HL, DELAY(-1,20ns,32ns),
+          EN & TRN_LH, DELAY(-1,14ns,26ns),
+          EN & TRN_HL, DELAY(-1,13ns,38ns),
+          IN & TRN_LH, DELAY(-1,11ns,20ns),
+          IN & TRN_HL, DELAY(-1,18ns,41ns),
+          DELAY(-1,21ns,42ns))}
+
+     Y1 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,12ns,18ns),
+          ENBAR & TRN_HL, DELAY(-1,20ns,32ns),
+          EN & TRN_LH, DELAY(-1,14ns,26ns),
+          EN & TRN_HL, DELAY(-1,13ns,38ns),
+          INA & TRN_LH, DELAY(-1,21ns,27ns),
+          INA & TRN_HL, DELAY(-1,20ns,39ns),
+          (INB | INC) & TRN_LH, DELAY(-1,11ns,20ns),
+          (INB | INC) & TRN_HL, DELAY(-1,18ns,41ns),
+          DELAY(-1,22ns,42ns))}
+
+     Y2 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,12ns,18ns),
+          ENBAR & TRN_HL, DELAY(-1,20ns,32ns),
+          EN & TRN_LH, DELAY(-1,14ns,26ns),
+          EN & TRN_HL, DELAY(-1,13ns,38ns),
+          INB & TRN_LH, DELAY(-1,21ns,27ns),
+          INB & TRN_HL, DELAY(-1,20ns,39ns),
+          (INA | INC) & TRN_LH, DELAY(-1,11ns,20ns),
+          (INA | INC) & TRN_HL, DELAY(-1,18ns,41ns),
+          DELAY(-1,22ns,42ns))}
+
+     Y3 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,12ns,18ns),
+          ENBAR & TRN_HL, DELAY(-1,20ns,32ns),
+          EN & TRN_LH, DELAY(-1,14ns,26ns),
+          EN & TRN_HL, DELAY(-1,13ns,38ns),
+          (INA | INB) & TRN_LH, DELAY(-1,21ns,27ns),
+          (INA | INB) & TRN_HL, DELAY(-1,20ns,39ns),
+          INC & TRN_LH, DELAY(-1,11ns,20ns),
+          INC & TRN_HL, DELAY(-1,18ns,41ns),
+          DELAY(-1,22ns,42ns))}
+
+     Y4 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,12ns,18ns),
+          ENBAR & TRN_HL, DELAY(-1,20ns,32ns),
+          EN & TRN_LH, DELAY(-1,14ns,26ns),
+          EN & TRN_HL, DELAY(-1,13ns,38ns),
+          INC & TRN_LH, DELAY(-1,21ns,27ns),
+          INC & TRN_HL, DELAY(-1,20ns,39ns),
+          (INB | INA) & TRN_LH, DELAY(-1,11ns,20ns),
+          (INB | INA) & TRN_HL, DELAY(-1,18ns,41ns),
+          DELAY(-1,22ns,42ns))}
+
+     Y5 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,12ns,18ns),
+          ENBAR & TRN_HL, DELAY(-1,20ns,32ns),
+          EN & TRN_LH, DELAY(-1,14ns,26ns),
+          EN & TRN_HL, DELAY(-1,13ns,38ns),
+          (INA | INC) & TRN_LH, DELAY(-1,21ns,27ns),
+          (INA | INC) & TRN_HL, DELAY(-1,20ns,39ns),
+          INB & TRN_LH, DELAY(-1,11ns,20ns),
+          INB & TRN_HL, DELAY(-1,18ns,41ns),
+          DELAY(-1,22ns,42ns))}
+
+     Y6 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,12ns,18ns),
+          ENBAR & TRN_HL, DELAY(-1,20ns,32ns),
+          EN & TRN_LH, DELAY(-1,14ns,26ns),
+          EN & TRN_HL, DELAY(-1,13ns,38ns),
+          (INB | INC) & TRN_LH, DELAY(-1,21ns,27ns),
+          (INB | INC) & TRN_HL, DELAY(-1,20ns,39ns),
+          INA & TRN_LH, DELAY(-1,11ns,20ns),
+          INA & TRN_HL, DELAY(-1,18ns,41ns),
+          DELAY(-1,22ns,42ns))}
+
+     Y7 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,12ns,18ns),
+          ENBAR & TRN_HL, DELAY(-1,20ns,32ns),
+          EN & TRN_LH, DELAY(-1,14ns,26ns),
+          EN & TRN_HL, DELAY(-1,13ns,38ns),
+          IN & TRN_LH, DELAY(-1,21ns,27ns),
+          IN & TRN_HL, DELAY(-1,20ns,39ns),
+          DELAY(-1,22ns,42ns))}
.ENDS 74LS138


.SUBCKT 74S138 A B C G1 G2ABAR G2BBAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(6,8) DPWR DGND
+ A B C G1 G2ABAR G2BBAR
+ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
+ D0_GATE IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+   ENAB = {G1 & ~G2ABAR & ~G2BBAR}
+   Y0O = {~(~A & ~B & ~C & ENAB)}
+   Y1O = {~(A & ~B & ~C & ENAB)}
+   Y2O = {~(~A & B & ~C & ENAB)}
+   Y3O = {~(A & B & ~C & ENAB)}
+   Y4O = {~(~A & ~B & C & ENAB)}
+   Y5O = {~(A & ~B & C & ENAB)}
+   Y6O = {~(~A & B & C & ENAB)}
+   Y7O = {~(A & B & C & ENAB)}
U2 PINDLY(8,0,6) DPWR DGND
+ Y0O Y1O Y2O Y3O Y4O Y5O Y6O Y7O
+ A B C G1 G2ABAR G2BBAR
+ Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+ IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
+     INA = {CHANGED(A,0)}
+     INB = {CHANGED(B,0)}
+     INC = {CHANGED(C,0)}
+     ENBAR = {CHANGED(G2ABAR,0) | CHANGED(G2BBAR,0)}
+     EN = {CHANGED(G1,0)}
+  PINDLY:
+     Y0 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,-1,10NS),
+          ENBAR & TRN_HL, DELAY(-1,-1,14NS),
+          EN & TRN_LH, DELAY(-1,-1,13NS),
+          EN & TRN_HL, DELAY(-1,-1,14NS),
+          IN & TRN_LH, DELAY(-1,-1,9NS),
+          IN & TRN_HL, DELAY(-1,-1,14NS),
+          DELAY(-1,-1,15NS))}
+     Y1 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,-1,10NS),
+          ENBAR & TRN_HL, DELAY(-1,-1,14NS),
+          EN & TRN_LH, DELAY(-1,-1,13NS),
+          EN & TRN_HL, DELAY(-1,-1,14NS),
+          INA & TRN_LH, DELAY(-1,-1,14NS),
+          INA & TRN_HL, DELAY(-1,-1,15NS),
+          (INB | INC) & TRN_LH, DELAY(-1,-1,9NS),
+          (INB | INC) & TRN_HL, DELAY(-1,-1,14NS),
+          DELAY(-1,-1,16NS))}
+     Y2 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,-1,10NS),
+          ENBAR & TRN_HL, DELAY(-1,-1,14NS),
+          EN & TRN_LH, DELAY(-1,-1,13NS),
+          EN & TRN_HL, DELAY(-1,-1,14NS),
+          INB & TRN_LH, DELAY(-1,-1,14NS),
+          INB & TRN_HL, DELAY(-1,-1,15NS),
+          (INA | INC) & TRN_LH, DELAY(-1,-1,9NS),
+          (INA | INC) & TRN_HL, DELAY(-1,-1,14NS),
+          DELAY(-1,-1,16NS))}
+     Y3 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,-1,10NS),
+          ENBAR & TRN_HL, DELAY(-1,-1,14NS),
+          EN & TRN_LH, DELAY(-1,-1,13NS),
+          EN & TRN_HL, DELAY(-1,-1,14NS),
+          (INA | INB) & TRN_LH, DELAY(-1,-1,14NS),
+          (INA | INB) & TRN_HL, DELAY(-1,-1,15NS),
+          INC & TRN_LH, DELAY(-1,-1,9NS),
+          INC & TRN_HL, DELAY(-1,-1,14NS),
+          DELAY(-1,-1,16NS))}
+     Y4 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,-1,10NS),
+          ENBAR & TRN_HL, DELAY(-1,-1,14NS),
+          EN & TRN_LH, DELAY(-1,-1,13NS),
+          EN & TRN_HL, DELAY(-1,-1,14NS),
+          INC & TRN_LH, DELAY(-1,-1,14NS),
+          INC & TRN_HL, DELAY(-1,-1,15NS),
+          (INB | INA) & TRN_LH, DELAY(-1,-1,9NS),
+          (INB | INA) & TRN_HL, DELAY(-1,-1,14NS),
+          DELAY(-1,-1,16NS))}
+     Y5 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,-1,10NS),
+          ENBAR & TRN_HL, DELAY(-1,-1,14NS),
+          EN & TRN_LH, DELAY(-1,-1,13NS),
+          EN & TRN_HL, DELAY(-1,-1,14NS),
+          (INA | INC) & TRN_LH, DELAY(-1,-1,14NS),
+          (INA | INC) & TRN_HL, DELAY(-1,-1,15NS),
+          INB & TRN_LH, DELAY(-1,-1,9NS),
+          INB & TRN_HL, DELAY(-1,-1,14NS),
+          DELAY(-1,-1,16NS))}
+     Y6 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,-1,10NS),
+          ENBAR & TRN_HL, DELAY(-1,-1,14NS),
+          EN & TRN_LH, DELAY(-1,-1,13NS),
+          EN & TRN_HL, DELAY(-1,-1,14NS),
+          (INB | INC) & TRN_LH, DELAY(-1,-1,14NS),
+          (INB | INC) & TRN_HL, DELAY(-1,-1,15NS),
+          INA & TRN_LH, DELAY(-1,-1,9NS),
+          INA & TRN_HL, DELAY(-1,-1,14NS),
+          DELAY(-1,-1,16NS))}
+     Y7 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,-1,10NS),
+          ENBAR & TRN_HL, DELAY(-1,-1,14NS),
+          EN & TRN_LH, DELAY(-1,-1,13NS),
+          EN & TRN_HL, DELAY(-1,-1,14NS),
+          IN & TRN_LH, DELAY(-1,-1,9NS),
+          IN & TRN_HL, DELAY(-1,-1,14NS),
+          DELAY(-1,-1,15NS))}
.ENDS 74S138


.SUBCKT 74S138A A B C G1 G2ABAR G2BBAR Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(6,8) DPWR DGND
+     A B C G1 G2ABAR G2BBAR
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     D0_GATE IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     enable = {(~G2ABAR) & (~G2BBAR) & G1}
+     Y0_O = {~(abar & bbar & cbar & enable)}
+     Y1_O = {~(A & bbar & cbar & enable)}
+     Y2_O = {~(abar & B & cbar & enable)}
+     Y3_O = {~(A & B & cbar & enable)}
+     Y4_O = {~(abar & bbar & C & enable)}
+     Y5_O = {~(A & bbar & C & enable)}
+     Y6_O = {~(abar & B & C & enable)}
+     Y7_O = {~(A & B & C & enable)}
U2DLY PINDLY(8,0,6) DPWR DGND
+     Y0_O Y1_O Y2_O Y3_O Y4_O Y5_O Y6_O Y7_O
+     A B C G1 G2ABAR G2BBAR
+     Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
+     IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A,0) | CHANGED(B,0) | CHANGED(C,0)}
+     INA = {CHANGED(A,0)}
+     INB = {CHANGED(B,0)}
+     INC = {CHANGED(C,0)}
+     ENBAR = {CHANGED(G2ABAR,0) | CHANGED(G2BBAR,0)}
+     EN = {CHANGED(G1,0)}
+
+  PINDLY:
+     Y0 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,5ns,8ns),
+          ENBAR & TRN_HL, DELAY(-1,7ns,11ns),
+          EN, DELAY(-1,7ns,11ns),
+          IN & TRN_LH, DELAY(-1,4.5ns,7ns),
+          IN & TRN_HL, DELAY(-1,7ns,10.5ns),
+          DELAY(-1,8ns,12ns))}
+
+     Y1 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,5ns,8ns),
+          ENBAR & TRN_HL, DELAY(-1,7ns,11ns),
+          EN, DELAY(-1,7ns,11ns),
+          INA & TRN_LH, DELAY(-1,7.5ns,12ns),
+          INA & TRN_HL, DELAY(-1,8ns,12ns),
+          (INB | INC) & TRN_LH, DELAY(-1,4.5ns,7ns),
+          (INB | INC) & TRN_HL, DELAY(-1,7ns,10.5ns),
+          DELAY(-1,9ns,13ns))}
+
+     Y2 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,5ns,8ns),
+          ENBAR & TRN_HL, DELAY(-1,7ns,11ns),
+          EN, DELAY(-1,7ns,11ns),
+          INB & TRN_LH, DELAY(-1,7.5ns,12ns),
+          INB & TRN_HL, DELAY(-1,8ns,12ns),
+          (INA | INC) & TRN_LH, DELAY(-1,4.5ns,7ns),
+          (INA | INC) & TRN_HL, DELAY(-1,7ns,10.5ns),
+          DELAY(-1,9ns,13ns))}
+
+     Y3 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,5ns,8ns),
+          ENBAR & TRN_HL, DELAY(-1,7ns,11ns),
+          EN, DELAY(-1,7ns,11ns),
+          (INA | INB) & TRN_LH, DELAY(-1,7.5ns,12ns),
+          (INA | INB) & TRN_HL, DELAY(-1,8ns,12ns),
+          INC & TRN_LH, DELAY(-1,4.5ns,7ns),
+          INC & TRN_HL, DELAY(-1,7ns,10.5ns),
+          DELAY(-1,9ns,13ns))}
+
+     Y4 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,5ns,8ns),
+          ENBAR & TRN_HL, DELAY(-1,7ns,11ns),
+          EN, DELAY(-1,7ns,11ns),
+          INC & TRN_LH, DELAY(-1,7.5ns,12ns),
+          INC & TRN_HL, DELAY(-1,8ns,12ns),
+          (INB | INA) & TRN_LH, DELAY(-1,4.5ns,7ns),
+          (INB | INA) & TRN_HL, DELAY(-1,7ns,10.5ns),
+          DELAY(-1,9ns,13ns))}
+
+     Y5 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,5ns,8ns),
+          ENBAR & TRN_HL, DELAY(-1,7ns,11ns),
+          EN, DELAY(-1,7ns,11ns),
+          (INA | INC) & TRN_LH, DELAY(-1,7.5ns,12ns),
+          (INA | INC) & TRN_HL, DELAY(-1,8ns,12ns),
+          INB & TRN_LH, DELAY(-1,4.5ns,7ns),
+          INB & TRN_HL, DELAY(-1,7ns,10.5ns),
+          DELAY(-1,9ns,13ns))}
+
+     Y6 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,5ns,8ns),
+          ENBAR & TRN_HL, DELAY(-1,7ns,11ns),
+          EN, DELAY(-1,7ns,11ns),
+          (INB | INC) & TRN_LH, DELAY(-1,7.5ns,12ns),
+          (INB | INC) & TRN_HL, DELAY(-1,8ns,12ns),
+          INA & TRN_LH, DELAY(-1,4.5ns,7ns),
+          INA & TRN_HL, DELAY(-1,7ns,10.5ns),
+          DELAY(-1,9ns,13ns))}
+
+     Y7 = {
+       CASE(
+          ENBAR & TRN_LH, DELAY(-1,5ns,8ns),
+          ENBAR & TRN_HL, DELAY(-1,7ns,11ns),
+          EN, DELAY(-1,7ns,11ns),
+          IN & TRN_LH, DELAY(-1,7.5ns,12ns),
+          IN & TRN_HL, DELAY(-1,8ns,12ns),
+          DELAY(-1,9ns,13ns))}
.ENDS 74S138A


.SUBCKT 74AC139 A0 A1 EABAR O0 O1 O2 O3
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(3,4) DPWR DGND
+     A0 A1 EABAR
+     O0_O O1_O O2_O O3_O
+     D0_GATE IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     ea = {~EABAR}
+     a0bar = {~A0}
+     a1bar = {~A1}
+     O0_O = {~(a0bar & a1bar & ea)}
+     O1_O = {~(A0 & a1bar & ea)}
+     O2_O = {~(a0bar & A1 & ea)}
+     O3_O = {~(A0 & A1 & ea)}
U2DLY PINDLY(4,0,3) DPWR DGND
+     O0_O O1_O O2_O O3_O
+     A0 A1 EABAR
+     O0 O1 O2 O3
+     IO_AC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A0,0) | CHANGED(A1,0)}
+     ENABLE = {CHANGED(EABAR,0)}
+
+  PINDLY:
+     O0 O1 O2 O3 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(3.5ns,7ns,8.5ns),
+          ENABLE & TRN_HL, DELAY(2.5ns,6ns,7.5ns),
+          IN & TRN_LH, DELAY(3ns,6.5ns,8.5ns),
+          IN & TRN_HL, DELAY(2.5ns,5.5ns,7.5ns),
+          DELAY(4.5ns,8ns,9.5ns))}
.ENDS 74AC139


.SUBCKT 74ACT139 A0 A1 EABAR O0 O1 O2 O3
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(3,4) DPWR DGND
+     A0 A1 EABAR
+     O0_O O1_O O2_O O3_O
+     D0_GATE IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     ea = {~EABAR}
+     a0bar = {~A0}
+     a1bar = {~A1}
+     O0_O = {~(a0bar & a1bar & ea)}
+     O1_O = {~(A0 & a1bar & ea)}
+     O2_O = {~(a0bar & A1 & ea)}
+     O3_O = {~(A0 & A1 & ea)}
U2DLY PINDLY(4,0,3) DPWR DGND
+     O0_O O1_O O2_O O3_O
+     A0 A1 EABAR
+     O0 O1 O2 O3
+     IO_ACT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A0,0) | CHANGED(A1,0)}
+     ENABLE = {CHANGED(EABAR,0)}
+
+  PINDLY:
+     O0 O1 O2 O3 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(2.5ns,7ns,10ns),
+          ENABLE & TRN_HL, DELAY(2ns,7ns,9.5ns),
+          IN & TRN_LH, DELAY(1.5ns,6ns,8.5ns),
+          IN & TRN_HL, DELAY(1.5ns,6ns,9.5ns),
+          DELAY(3.5ns,8ns,11ns))}
.ENDS 74ACT139


.SUBCKT 74ALS139 1A 1B 1GB 1Y0 1Y1 1Y2 1Y3
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(3,4) DPWR DGND
+     1A 1B 1GB
+     1Y0_O 1Y1_O 1Y2_O 1Y3_O
+     D0_GATE IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     1g = {~1GB}
+     abar = {~1A}
+     bbar = {~1B}
+     1Y0_O = {~(abar & bbar & 1g)}
+     1Y1_O = {~(1A & bbar & 1g)}
+     1Y2_O = {~(abar & 1B & 1g)}
+     1Y3_O = {~(1A & 1B & 1g)}
U2DLY PINDLY(4,0,3) DPWR DGND
+     1Y0_O 1Y1_O 1Y2_O 1Y3_O
+     1A 1B 1GB
+     1Y0 1Y1 1Y2 1Y3
+     IO_ALS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(1A,0) | CHANGED(1B,0)}
+     ENABLE = {CHANGED(1GB,0)}
+
+  PINDLY:
+     1Y0 1Y1 1Y2 1Y3 = {
+       CASE(
+          TRN_LH, DELAY(3ns,9ns,14ns),
+          ENABLE & TRN_HL, DELAY(3ns,9ns,15ns),
+          IN & TRN_HL, DELAY(3ns,9ns,14ns),
+          DELAY(4ns,10ns,16ns))}
.ENDS 74ALS139


.SUBCKT 74AS139 1A 1B 1GB 1Y0 1Y1 1Y2 1Y3
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(3,4) DPWR DGND
+     1A 1B 1GB
+     1Y0_O 1Y1_O 1Y2_O 1Y3_O
+     D0_GATE IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     1g = {~1GB}
+     abar = {~1A}
+     bbar = {~1B}
+     1Y0_O = {~(abar & bbar & 1g)}
+     1Y1_O = {~(1A & bbar & 1g)}
+     1Y2_O = {~(abar & 1B & 1g)}
+     1Y3_O = {~(1A & 1B & 1g)}
U2DLY PINDLY(4,0,3) DPWR DGND
+     1Y0_O 1Y1_O 1Y2_O 1Y3_O
+     1A 1B 1GB
+     1Y0 1Y1 1Y2 1Y3
+     IO_AS00 MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(1A,0) | CHANGED(1B,0)}
+     ENABLE = {CHANGED(1GB,0)}
+
+  PINDLY:
+     1Y0 1Y1 1Y2 1Y3 = {
+       CASE(
+          TRN_LH, DELAY(-1,5.5ns,-1),
+          ENABLE & TRN_HL, DELAY(-1,5ns,-1),
+          IN & TRN_HL, DELAY(-1,6ns,-1),
+          DELAY(-1,7ns,-1))}
.ENDS 74AS139


.SUBCKT 74F139 A0 A1 EABAR Q0 Q1 Q2 Q3
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(3,4) DPWR DGND
+     A0 A1 EABAR
+     Q0_O Q1_O Q2_O Q3_O
+     D0_GATE IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     ea = {~EABAR}
+     a0bar = {~A0}
+     a1bar = {~A1}
+     Q0_O = {~(a0bar & a1bar & ea)}
+     Q1_O = {~(A0 & a1bar & ea)}
+     Q2_O = {~(a0bar & A1 & ea)}
+     Q3_O = {~(A0 & A1 & ea)}
U2DLY PINDLY(4,0,3) DPWR DGND
+     Q0_O Q1_O Q2_O Q3_O
+     A0 A1 EABAR
+     Q0 Q1 Q2 Q3
+     IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(A0,0) | CHANGED(A1,0)}
+     ENABLE = {CHANGED(EABAR,0)}
+
+  PINDLY:
+     Q0 Q1 Q2 Q3 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(3.5ns,5.4ns,7ns),
+          ENABLE & TRN_HL, DELAY(3ns,4.7ns,6.5ns),
+          IN & TRN_LH, DELAY(3.5ns,5.3ns,7ns),
+          IN & TRN_HL, DELAY(4ns,6.1ns,8ns),
+          DELAY(5ns,7.1ns,9ns))}
.ENDS 74F139


.SUBCKT 74HC139 1A 1B 1GB 1Y0 1Y1 1Y2 1Y3
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(3,4) DPWR DGND
+     1A 1B 1GB
+     1Y0_O 1Y1_O 1Y2_O 1Y3_O
+     D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     1g = {~1GB}
+     abar = {~1A}
+     bbar = {~1B}
+     1Y0_O = {~(abar & bbar & 1g)}
+     1Y1_O = {~(1A & bbar & 1g)}
+     1Y2_O = {~(abar & 1B & 1g)}
+     1Y3_O = {~(1A & 1B & 1g)}
U2DLY PINDLY(4,0,3) DPWR DGND
+     1Y0_O 1Y1_O 1Y2_O 1Y3_O
+     1A 1B 1GB
+     1Y0 1Y1 1Y2 1Y3
+     IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(1A,0) | CHANGED(1B,0)}
+     ENABLE = {CHANGED(1GB,0)}
+
+  PINDLY:
+     1Y0 1Y1 1Y2 1Y3 = {
+       CASE(
+          ENABLE, DELAY(-1,11ns,35ns),
+          IN, DELAY(-1,14ns,35ns),
+          DELAY(-1,15ns,36ns))}
.ENDS 74HC139


.SUBCKT 74HC139A A0A A1A SELA Y0A Y1A Y2A Y3A
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(3,4) DPWR DGND
+ A0A A1A SELA
+ Y0A Y1A Y2A Y3A
+ DLY_HC139A IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+   Y0A = {~(~SELA & ~A0A & ~A1A)}
+   Y1A = {~(~SELA & A0A & ~A1A)}
+   Y2A = {~(~SELA & ~A0A & A1A)}
+   Y3A = {~(~SELA & A0A & A1A)}
.MODEL DLY_HC139A UGATE(TPLHMX=23NS TPHLMX=23NS)
.ENDS 74HC139A


.SUBCKT 74HCT139 1A 1B 1GB 1Y0 1Y1 1Y2 1Y3
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(3,4) DPWR DGND
+     1A 1B 1GB
+     1Y0_O 1Y1_O 1Y2_O 1Y3_O
+     D0_GATE IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     1g = {~1GB}
+     abar = {~1A}
+     bbar = {~1B}
+     1Y0_O = {~(abar & bbar & 1g)}
+     1Y1_O = {~(1A & bbar & 1g)}
+     1Y2_O = {~(abar & 1B & 1g)}
+     1Y3_O = {~(1A & 1B & 1g)}
U2DLY PINDLY(4,0,3) DPWR DGND
+     1Y0_O 1Y1_O 1Y2_O 1Y3_O
+     1A 1B 1GB
+     1Y0 1Y1 1Y2 1Y3
+     IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(1A,0) | CHANGED(1B,0)}
+     ENABLE = {CHANGED(1GB,0)}
+
+  PINDLY:
+     1Y0 1Y1 1Y2 1Y3 = {
+       CASE(
+          ENABLE, DELAY(-1,11ns,34ns),
+          IN, DELAY(-1,14ns,34ns),
+          DELAY(-1,15ns,35ns))}
.ENDS 74HCT139


.SUBCKT 74LS139 A1 B1 G1 1Y0 1Y1 1Y2 1Y3
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(3,4) DPWR DGND
+ A1 B1 G1
+ 1Y0O 1Y1O 1Y2O 1Y3O
+ D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+   1Y0O = {~(~A1 & ~B1 & ~G1)}
+   1Y1O = {~(A1 & ~B1 & ~G1)}
+   1Y2O = {~(~A1 & B1 & ~G1)}
+   1Y3O = {~(A1 & B1 & ~G1)}
U2 PINDLY(4,0,3) DPWR DGND
+ 1Y0O 1Y1O 1Y2O 1Y3O
+ A1 B1 G1
+ 1Y0 1Y1 1Y2 1Y3
+ IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+     IN = {CHANGED(A1,0) | CHANGED(B1,0)}
+     ENABLE = {CHANGED(G1,0)}
+  PINDLY:
+     1Y0 1Y1 1Y2 1Y3 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(-1,-1,18NS),
+          ENABLE & TRN_HL, DELAY(-1,-1,24NS),
+          IN & TRN_LH, DELAY(-1,-1,18NS),
+          IN & TRN_HL, DELAY(-1,-1,27NS),
+          DELAY(-1,-1,28NS))}
.ENDS 74LS139


.SUBCKT 74LS139A 1A 1B 1GB 1Y0 1Y1 1Y2 1Y3
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(3,4) DPWR DGND
+     1A 1B 1GB
+     1Y0_O 1Y1_O 1Y2_O 1Y3_O
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     1g = {~1GB}
+     abar = {~1A}
+     bbar = {~1B}
+     1Y0_O = {~(abar & bbar & 1g)}
+     1Y1_O = {~(1A & bbar & 1g)}
+     1Y2_O = {~(abar & 1B & 1g)}
+     1Y3_O = {~(1A & 1B & 1g)}
U2DLY PINDLY(4,0,3) DPWR DGND
+     1Y0_O 1Y1_O 1Y2_O 1Y3_O
+     1A 1B 1GB
+     1Y0 1Y1 1Y2 1Y3
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(1A,0) | CHANGED(1B,0)}
+     INA = {CHANGED(1A,0)}
+     INB = {CHANGED(1B,0)}
+     ENABLE = {CHANGED(1GB,0)}
+
+  PINDLY:
+     1Y0 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(-1,16ns,24ns),
+          ENABLE & TRN_HL, DELAY(-1,21ns,32ns),
+          IN & TRN_LH, DELAY(-1,13ns,20ns),
+          IN & TRN_HL, DELAY(-1,22ns,33ns),
+          DELAY(-1,23ns,34ns))}
+
+     1Y1 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(-1,16ns,24ns),
+          ENABLE & TRN_HL, DELAY(-1,21ns,32ns),
+          INA & TRN_LH, DELAY(-1,18ns,29ns),
+          INA & TRN_HL, DELAY(-1,25ns,38ns),
+          INB & TRN_LH, DELAY(-1,13ns,20ns),
+          INB & TRN_HL, DELAY(-1,22ns,33ns),
+          DELAY(-1,23ns,34ns))}
+
+     1Y2 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(-1,16ns,24ns),
+          ENABLE & TRN_HL, DELAY(-1,21ns,32ns),
+          INB & TRN_LH, DELAY(-1,18ns,29ns),
+          INB & TRN_HL, DELAY(-1,25ns,38ns),
+          INA & TRN_LH, DELAY(-1,13ns,20ns),
+          INA & TRN_HL, DELAY(-1,22ns,33ns),
+          DELAY(-1,23ns,34ns))}
+
+     1Y3 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(-1,16ns,24ns),
+          ENABLE & TRN_HL, DELAY(-1,21ns,32ns),
+          IN & TRN_LH, DELAY(-1,18ns,29ns),
+          IN & TRN_HL, DELAY(-1,25ns,38ns),
+          DELAY(-1,23ns,34ns))}
.ENDS 74LS139A


.SUBCKT 74S139 A1 B1 G1 1Y0 1Y1 1Y2 1Y3
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(3,4) DPWR DGND
+ A1 B1 G1
+ 1Y0O 1Y1O 1Y2O 1Y3O
+ D0_GATE IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+   1Y0O = {~(~A1 & ~B1 & ~G1)}
+   1Y1O = {~(A1 & ~B1 & ~G1)}
+   1Y2O = {~(~A1 & B1 & ~G1)}
+   1Y3O = {~(A1 & B1 & ~G1)}
U2 PINDLY(4,0,3) DPWR DGND
+ 1Y0O 1Y1O 1Y2O 1Y3O
+ A1 B1 G1
+ 1Y0 1Y1 1Y2 1Y3
+ IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+     IN = {CHANGED(A1,0) | CHANGED(B1,0)}
+     INA = {CHANGED(A1,0)}
+     INB = {CHANGED(B1,0)}
+     ENABLE = {CHANGED(G1,0)}
+  PINDLY:
+     1Y0 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(-1,-1,10NS),
+          ENABLE & TRN_HL, DELAY(-1,-1,13NS),
+          IN & TRN_LH, DELAY(-1,-1,10NS),
+          IN & TRN_HL, DELAY(-1,-1,13NS),
+          DELAY(-1,-1,14NS))}
+     1Y1 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(-1,-1,10NS),
+          ENABLE & TRN_HL, DELAY(-1,-1,13NS),
+          INA & TRN_LH, DELAY(-1,-1,13NS),
+          INA & TRN_HL, DELAY(-1,-1,15NS),
+          INB & TRN_LH, DELAY(-1,-1,10NS),
+          INB & TRN_HL, DELAY(-1,-1,13NS),
+          DELAY(-1,-1,16NS))}
+     1Y2 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(-1,-1,10NS),
+          ENABLE & TRN_HL, DELAY(-1,-1,13NS),
+          INB & TRN_LH, DELAY(-1,-1,13NS),
+          INB & TRN_HL, DELAY(-1,-1,15NS),
+          INA & TRN_LH, DELAY(-1,-1,10NS),
+          INA & TRN_HL, DELAY(-1,-1,13NS),
+          DELAY(-1,-1,16NS))}
+     1Y3 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(-1,-1,10NS),
+          ENABLE & TRN_HL, DELAY(-1,-1,13NS),
+          IN & TRN_LH, DELAY(-1,-1,13NS),
+          IN & TRN_HL, DELAY(-1,-1,15NS),
+          DELAY(-1,-1,16NS))}
.ENDS 74S139


.SUBCKT 74S139A 1A 1B 1GB 1Y0 1Y1 1Y2 1Y3
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(3,4) DPWR DGND
+     1A 1B 1GB
+     1Y0_O 1Y1_O 1Y2_O 1Y3_O
+     D0_GATE IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     1g = {~1GB}
+     abar = {~1A}
+     bbar = {~1B}
+     1Y0_O = {~(abar & bbar & 1g)}
+     1Y1_O = {~(1A & bbar & 1g)}
+     1Y2_O = {~(abar & 1B & 1g)}
+     1Y3_O = {~(1A & 1B & 1g)}
U2DLY PINDLY(4,0,3) DPWR DGND
+     1Y0_O 1Y1_O 1Y2_O 1Y3_O
+     1A 1B 1GB
+     1Y0 1Y1 1Y2 1Y3
+     IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN = {CHANGED(1A,0) | CHANGED(1B,0)}
+     INA = {CHANGED(1A,0)}
+     INB = {CHANGED(1B,0)}
+     ENABLE = {CHANGED(1GB,0)}
+
+  PINDLY:
+     1Y0 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(-1,5ns,8ns),
+          ENABLE & TRN_HL, DELAY(-1,6.5ns,10ns),
+          IN & TRN_LH, DELAY(-1,5ns,7.5ns),
+          IN & TRN_HL, DELAY(-1,6.5ns,10ns),
+          DELAY(-1,7.5ns,11ns))}
+
+     1Y1 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(-1,5ns,8ns),
+          ENABLE & TRN_HL, DELAY(-1,6.5ns,10ns),
+          INA & TRN_LH, DELAY(-1,7ns,12ns),
+          INA & TRN_HL, DELAY(-1,8ns,12ns),
+          INB & TRN_LH, DELAY(-1,5ns,7.5ns),
+          INB & TRN_HL, DELAY(-1,6.5ns,10ns),
+          DELAY(-1,9ns,13ns))}
+
+     1Y2 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(-1,5ns,8ns),
+          ENABLE & TRN_HL, DELAY(-1,6.5ns,10ns),
+          INB & TRN_LH, DELAY(-1,7ns,12ns),
+          INB & TRN_HL, DELAY(-1,8ns,12ns),
+          INA & TRN_LH, DELAY(-1,5ns,7.5ns),
+          INA & TRN_HL, DELAY(-1,6.5ns,10ns),
+          DELAY(-1,9ns,13ns))}
+
+     1Y3 = {
+       CASE(
+          ENABLE & TRN_LH, DELAY(-1,5ns,8ns),
+          ENABLE & TRN_HL, DELAY(-1,6.5ns,10ns),
+          IN & TRN_LH, DELAY(-1,7ns,12ns),
+          IN & TRN_HL, DELAY(-1,8ns,12ns),
+          DELAY(-1,9ns,13ns))}
.ENDS 74S139A


.SUBCKT 74S140 1A 1B 1C 1D 1Y
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1 nand(4) DPWR DGND
+     1A 1B 1C 1D 1Y
+     DLY_S140 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
.model DLY_S140 ugate (tplhTY=4ns tplhMX=6.5ns tphlTY=4ns tphlMX=6.5ns)
.ENDS 74S140


.SUBCKT 74143	
+ SCEIBAR PCEIBAR CLK CLRBAR STRBBAR RBIBAR BI BI/RBOBAR DPIN
+ MAX QA QB QC QD A B C D E F G DPOUT
+ OPTIONAL: DPWR=$G_DPWR DGND=$G_DGND
+ PARAMS: MNTYMXDLY=0 IO_LEVEL=0
U1 LOGICEXP(24,15) DPWR DGND
+ SCEIBAR PCEIBAR CLK CLRBAR STRBBAR TQA TQB TQC TQD TQABAR TQBBAR TQCBAR
+ TQDBAR QAO QBO QCO QDO QABARO QBBARO QCBARO QDBARO RBIBAR BI DPIN
+ CLKA CLKB CLKC CLKD LATCH MAXO BI/RBOBARO AO BO CO DO EO FO GO DPOUTO
+ D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ LOGIC:
+   CLKA = {~CLK & (~SCEIBAR & ~PCEIBAR)}
+   CLKB = {~CLK & (~SCEIBAR & ~PCEIBAR) & TQA & TQDBAR}
+   CLKC = {~CLK & (~SCEIBAR & ~PCEIBAR) & TQA & TQB}
+   CLKD = {~CLK & (~SCEIBAR & ~PCEIBAR) & TQA & ((TQB & TQC) | TQD)}
+   LATCH = {~STRBBAR}
+   NAND1 = {~(QABARO & QBBARO & QCBARO & QDBARO)}
+   NAND2 = {~(QAO & QBBARO & QCBARO & QDBARO)}
+   NAND3 = {~(QABARO & QBO & QCBARO & QDBARO)}
+   NAND4 = {~(QAO & QBO & QCBARO & QDBARO)}
+   NAND5 = {~(QABARO & QBBARO & QCO & QDBARO)}
+   NAND6 = {~(QAO & QBBARO & QCO & QDBARO)}
+   NAND7 = {~(QABARO & QBO & QCO & QDBARO)}
+   NAND8 = {~(QAO & QBO & QCO & QDBARO)}
+   NAND9 = {~(QAO & QBBARO & QCBARO & QDO)}
+   MAXO = {~(~SCEIBAR & TQA & TQD)}
+   BI/RBOBARO = {~(BI | (~RBIBAR & QABARO & QBBARO & QCBARO & QDBARO))}
+   AO = {~(NAND2 & NAND5 & BI/RBOBARO)}
+   BO = {~(NAND6 & NAND7 & BI/RBOBARO)}
+   CO = {~(NAND3 & BI/RBOBARO)}
+   DO = {~(NAND2 & NAND5 & NAND8 & BI/RBOBARO)}
+   EO = {~(NAND2 & NAND4 & NAND5 & NAND6 & NAND8 & NAND9 & BI/RBOBARO)}
+   FO = {~(NAND2 & NAND3 & NAND4 & NAND8 & BI/RBOBARO)}
+   GO = {~(NAND1 & NAND2 & NAND8 & BI/RBOBARO)}
+   DPOUTO = {~(BI/RBOBARO & DPIN)}
U2 JKFF(1) DPWR DGND
+ $D_HI CLRBAR CLKA
+ $D_HI $D_HI TQA TQABAR
+ D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U3 JKFF(1) DPWR DGND
+ $D_HI CLRBAR CLKB
+ $D_HI $D_HI TQB TQBBAR
+ D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U4 JKFF(1) DPWR DGND
+ $D_HI CLRBAR CLKC
+ $D_HI $D_HI TQC TQCBAR
+ D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U5 JKFF(1) DPWR DGND
+ $D_HI CLRBAR CLKD
+ $D_HI $D_HI TQD TQDBAR
+ D0_EFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U6 DLTCH(4) DPWR DGND
+ $D_HI $D_HI LATCH
+ TQA TQB TQC TQD
+ QAO QBO QCO QDO
+ QABARO QBBARO QCBARO QDBARO
+ D0_GFF IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
U7 PINDLY(14,0,2) DPWR DGND
+ MAXO QAO QBO QCO QDO BI/RBOBARO AO BO CO DO EO FO GO DPOUTO
+ SCEIBAR CLK
+ MAX QA QB QC QD BI/RBOBAR A B C D E F G DPOUT
+ IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+ BOOLEAN:
+   SERIAL = {CHANGED(SCEIBAR,0)}
+   EDGE = {CHANGED(CLK,0)}
+ PINDLY:
+     QA QB QC QD = {
+       CASE(
+        EDGE & (TRN_LH | TRN_HL), DELAY(-1,28NS,45NS),
+        DELAY(-1,29NS,46NS))}
+     MAX = {
+       CASE(
+        SERIAL & TRN_LH, DELAY(-1,12NS,20NS),
+        SERIAL & TRN_LH, DELAY(-1,23NS,35NS),
+        EDGE & TRN_LH, DELAY(-1,26NS,40NS),
+        EDGE & TRN_LH, DELAY(-1,29NS,45NS),
+        DELAY(-1,30NS,46NS))}
+      BI/RBOBAR A B C D E F G DPOUT = {
+        CASE(
+           DELAY(-1,30NS,46NS))}
U8 CONSTRAINT(4) DPWR DGND
+ CLK CLRBAR SCEIBAR PCEIBAR
+ IO_STD IO_LEVEL={IO_LEVEL}
+ WIDTH:
+  NODE = CLK
+  MIN_LO = 55NS
+  MIN_HI = 25NS
+ WIDTH:
+  NODE = CLRBAR
+  MIN_LO = 25NS
+  MIN_HI = 25NS
+ SETUP_HOLD:
+  CLOCK LH = CLK
+  DATA(2) = SCEIBAR PCEIBAR
+  SETUPTIME = 30NS
+ SETUP_HOLD:
+  CLOCK LH = CLK
+  DATA(1) = CLRBAR
+  SETUPTIME_HI = 60NS
.ENDS 74143


.SUBCKT 74145 A B C D O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(4,10) DPWR DGND
+     A B C D
+     O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     dbar = {~D}
+     O0_O = {~(abar & bbar & cbar & dbar)}
+     O1_O = {~(A & bbar & cbar & dbar)}
+     O2_O = {~(abar & B & cbar & dbar)}
+     O3_O = {~(A & B & cbar & dbar)}
+     O4_O = {~(abar & bbar & C & dbar)}
+     O5_O = {~(A & bbar & C & dbar)}
+     O6_O = {~(abar & B & C & dbar)}
+     O7_O = {~(A & B & C & dbar)}
+     O8_O = {~(abar & bbar & cbar & D)}
+     O9_O = {~(A & bbar & cbar & D)}
U2DLY PINDLY(10,0,0) DPWR DGND
+     O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+     O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 = {
+        CASE(
+          DELAY(-1,-1,50ns))}
.ENDS 74145


.SUBCKT 74LS145 A B C D O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(4,10) DPWR DGND
+     A B C D
+     O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     abar = {~A}
+     bbar = {~B}
+     cbar = {~C}
+     dbar = {~D}
+     O0_O = {~(abar & bbar & cbar & dbar)}
+     O1_O = {~(A & bbar & cbar & dbar)}
+     O2_O = {~(abar & B & cbar & dbar)}
+     O3_O = {~(A & B & cbar & dbar)}
+     O4_O = {~(abar & bbar & C & dbar)}
+     O5_O = {~(A & bbar & C & dbar)}
+     O6_O = {~(abar & B & C & dbar)}
+     O7_O = {~(A & B & C & dbar)}
+     O8_O = {~(abar & bbar & cbar & D)}
+     O9_O = {~(A & bbar & cbar & D)}
U2DLY PINDLY(10,0,0) DPWR DGND
+     O0_O O1_O O2_O O3_O O4_O O5_O O6_O O7_O O8_O O9_O
+     O0 O1 O2 O3 O4 O5 O6 O7 O8 O9
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 = {
+        CASE(
+          DELAY(-1,-1,50ns))}
.ENDS 74LS145


.SUBCKT 74147 I1 I2 I3 I4 I5 I6 I7 I8 I9 A B C D
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(9,4) DPWR DGND
+     I1 I2 I3 I4 I5 I6 I7 I8 I9
+     A_O B_O C_O D_O
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     i1bar = {~I1}
+     i2bar = {~I2}
+     i3bar = {~I3}
+     i4bar = {~I4}
+     i5bar = {~I5}
+     i6bar = {~I6}
+     i7bar = {~I7}
+     i8bar = {~I8}
+     i9bar = {~I9}
+     nor89 = {~(i8bar | i9bar)}
+     A_O = {~((i1bar & I2 & I4 & I6 & nor89) | (i3bar & I4 & I6 & nor89) | (i5bar & I6 & nor89) |
+                (i7bar & nor89) | i9bar)}
+     B_O = {~((i2bar & I4 & I5 & nor89) | (i3bar & I4 & I5 & nor89) | (i6bar & nor89) | 
+                (i7bar & nor89))}
+     C_O = {~((i4bar & nor89) | (i5bar & nor89) | (i6bar & nor89) | (i7bar & nor89))}
+     D_O = {~(i8bar | i9bar)}
U2DLY PINDLY(4,0,9) DPWR DGND
+     A_O B_O C_O D_O
+     I1 I2 I3 I4 I5 I6 I7 I8 I9
+     A B C D
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN1 = {CHANGED(I1,0) & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1 & I8=='1 & 
+               I9=='1}
+     IN2 = {CHANGED(I2,0) & I1=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1 & I8=='1 & 
+               I9=='1}
+     IN3 = {CHANGED(I3,0) & I1=='1 & I2=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1 & I8=='1 & 
+               I9=='1}
+     IN4 = {CHANGED(I4,0) & I1=='1 & I2=='1 & I3=='1 & I5=='1 & I6=='1 & I7=='1 & I8=='1 & 
+               I9=='1}
+     IN5 = {CHANGED(I5,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I6=='1 & I7=='1 & I8=='1 & 
+               I9=='1}
+     IN6 = {CHANGED(I6,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I7=='1 & I8=='1 & 
+               I9=='1}
+     IN7 = {CHANGED(I7,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I8=='1 & 
+               I9=='1}
+     IN8 = {CHANGED(I8,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1 & 
+               I9=='1}
+     IN9 = {CHANGED(I9,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1 & 
+               I8=='1}   
+     IN = {IN1 | IN2 | IN3 | IN4 | IN5 | IN6 | IN7 | IN8 | IN9}
+
+  PINDLY:
+     A B C = {
+       CASE(
+         IN & TRN_LH, DELAY(-1,9ns,14ns),
+         IN & TRN_HL, DELAY(-1,7ns,11ns),
+         TRN_LH, DELAY(-1,13ns,19ns),
+         TRN_HL, DELAY(-1,12ns,19ns),
+         DELAY(-1,14ns,20ns))}
+
+     D = {
+       CASE(
+         (IN8 | IN9) & TRN_LH, DELAY(-1,9ns,14ns),
+         (IN8 | IN9) & TRN_HL, DELAY(-1,7ns,11ns),
+         TRN_LH, DELAY(-1,13ns,19ns),
+         TRN_HL, DELAY(-1,12ns,19ns),
+         DELAY(-1,14ns,20ns))}
.ENDS 74147


.SUBCKT 74HC147 I1 I2 I3 I4 I5 I6 I7 I8 I9 A B C D
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(9,4) DPWR DGND
+     I1 I2 I3 I4 I5 I6 I7 I8 I9
+     A_O B_O C_O D_O
+     D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     i1bar = {~I1}
+     i2bar = {~I2}
+     i3bar = {~I3}
+     i4bar = {~I4}
+     i5bar = {~I5}
+     i6bar = {~I6}
+     i7bar = {~I7}
+     i8bar = {~I8}
+     i9bar = {~I9}
+     nor89 = {~(i8bar | i9bar)}
+     A_O = {~((i1bar & I2 & I4 & I6 & nor89) | (i3bar & I4 & I6 & nor89) | (i5bar & I6 & nor89) |
+                (i7bar & nor89) | i9bar)}
+     B_O = {~((i2bar & I4 & I5 & nor89) | (i3bar & I4 & I5 & nor89) | (i6bar & nor89) | 
+                (i7bar & nor89))}
+     C_O = {~((i4bar & nor89) | (i5bar & nor89) | (i6bar & nor89) | (i7bar & nor89))}
+     D_O = {~(i8bar | i9bar)}
U2DLY PINDLY(4,0,9) DPWR DGND
+     A_O B_O C_O D_O
+     I1 I2 I3 I4 I5 I6 I7 I8 I9
+     A B C D
+     IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     A B C D = {
+       CASE(
+         DELAY(-1,25ns,38ns))}
.ENDS 74HC147


.SUBCKT 74HCT147 A0 A1 A2 A3 A4 A5 A6 A7 A8 Y0 Y1 Y2 Y3
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(9,4) DPWR DGND
+     A0 A1 A2 A3 A4 A5 A6 A7 A8
+     Y0_O Y1_O Y2_O Y3_O
+     D0_GATE IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     a0bar = {~A0}
+     a1bar = {~A1}
+     a2bar = {~A2}
+     a3bar = {~A3}
+     a4bar = {~A4}
+     a5bar = {~A5}
+     a6bar = {~A6}
+     a7bar = {~A7}
+     a8bar = {~A8}
+     nor78 = {~(a7bar | a8bar)}
+     Y0_O = {~((a0bar & A1 & A3 & A5 & nor78) | (a2bar & A3 & A5 & nor78) | 
+                (a4bar & A5 & nor78) | (a6bar & nor78) | a8bar)}
+     Y1_O = {~((a1bar & A3 & A4 & nor78) | (a2bar & A3 & A4 & nor78) | (a5bar & nor78) | 
+                (a6bar & nor78))}
+     Y2_O = {~((a3bar & nor78) | (a4bar & nor78) | (a5bar & nor78) | (a6bar & nor78))}
+     Y3_O = {~(a7bar | a8bar)}
U2DLY PINDLY(4,0,9) DPWR DGND
+     Y0_O Y1_O Y2_O Y3_O
+     A0 A1 A2 A3 A4 A5 A6 A7 A8
+     Y0 Y1 Y2 Y3
+     IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  PINDLY:
+     Y0 Y1 Y2 Y3 = {
+       CASE(
+         DELAY(-1,18ns,32ns))}
.ENDS 74HCT147


.SUBCKT 74LS147 I1 I2 I3 I4 I5 I6 I7 I8 I9 A B C D
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(9,4) DPWR DGND
+     I1 I2 I3 I4 I5 I6 I7 I8 I9
+     A_O B_O C_O D_O
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     i1bar = {~I1}
+     i2bar = {~I2}
+     i3bar = {~I3}
+     i4bar = {~I4}
+     i5bar = {~I5}
+     i6bar = {~I6}
+     i7bar = {~I7}
+     i8bar = {~I8}
+     i9bar = {~I9}
+     nor89 = {~(i8bar | i9bar)}
+     A_O = {~((i1bar & I2 & I4 & I6 & nor89) | (i3bar & I4 & I6 & nor89) | (i5bar & I6 & nor89) |
+                (i7bar & nor89) | i9bar)}
+     B_O = {~((i2bar & I4 & I5 & nor89) | (i3bar & I4 & I5 & nor89) | (i6bar & nor89) | 
+                (i7bar & nor89))}
+     C_O = {~((i4bar & nor89) | (i5bar & nor89) | (i6bar & nor89) | (i7bar & nor89))}
+     D_O = {~(i8bar | i9bar)}
U2DLY PINDLY(4,0,9) DPWR DGND
+     A_O B_O C_O D_O
+     I1 I2 I3 I4 I5 I6 I7 I8 I9
+     A B C D
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     IN1 = {CHANGED(I1,0) & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1 & I8=='1 & 
+               I9=='1}
+     IN2 = {CHANGED(I2,0) & I1=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1 & I8=='1 & 
+               I9=='1}
+     IN3 = {CHANGED(I3,0) & I1=='1 & I2=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1 & I8=='1 & 
+               I9=='1}
+     IN4 = {CHANGED(I4,0) & I1=='1 & I2=='1 & I3=='1 & I5=='1 & I6=='1 & I7=='1 & I8=='1 & 
+               I9=='1}
+     IN5 = {CHANGED(I5,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I6=='1 & I7=='1 & I8=='1 & 
+               I9=='1}
+     IN6 = {CHANGED(I6,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I7=='1 & I8=='1 & 
+               I9=='1}
+     IN7 = {CHANGED(I7,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I8=='1 & 
+               I9=='1}
+     IN8 = {CHANGED(I8,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1 & 
+               I9=='1}
+     IN9 = {CHANGED(I9,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1 & 
+               I8=='1}   
+     IN = {IN1 | IN2 | IN3 | IN4 | IN5 | IN6 | IN7 | IN8 | IN9}
+
+  PINDLY:
+     A B C = {
+       CASE(
+         IN, DELAY(-1,12ns,18ns),
+         TRN_LH, DELAY(-1,21ns,33ns),
+         TRN_HL, DELAY(-1,15ns,23ns),
+         DELAY(-1,22ns,34ns))}
+
+     D = {
+       CASE(
+         (IN8 | IN9), DELAY(-1,12ns,18ns),
+         TRN_LH, DELAY(-1,21ns,33ns),
+         TRN_HL, DELAY(-1,15ns,23ns),
+         DELAY(-1,22ns,34ns))}
.ENDS 74LS147


.SUBCKT 74148 I0 I1 I2 I3 I4 I5 I6 I7 EI A0 A1 A2 EO GS
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(9,5) DPWR DGND
+     I0 I1 I2 I3 I4 I5 I6 I7 EI
+     A0_O A1_O A2_O EO_O GS_O
+     D0_GATE IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     i1bar = {~I1}
+     i2bar = {~I2}
+     i3bar = {~I3}
+     i4bar = {~I4}
+     i5bar = {~I5}
+     i6bar = {~I6}
+     i7bar = {~I7}
+     eibar = {~EI}
+     EO_O = {~(I0 & I1 & I2 & I3 & I4 & I5 & I6 & I7 & eibar)}
+     GS_O = {~(EO_O & eibar)}
+     A0_O = {~((i1bar & I2 & I4 & I6 & eibar) | (i3bar & I4 & I6 & eibar) | (i5bar & I6 & eibar) |
+                  (i7bar & eibar))}
+     A1_O = {~((i2bar & I4 & I5 & eibar) | (i3bar & I4 & I5 & eibar) | (i6bar & eibar) |
+                  (i7bar & eibar))}
+     A2_O = {~((i4bar & eibar) | (i5bar & eibar) | (i6bar & eibar) | (i7bar & eibar))}
U2DLY PINDLY(5,0,9) DPWR DGND
+     A0_O A1_O A2_O EO_O GS_O
+     I0 I1 I2 I3 I4 I5 I6 I7 EI
+     A0 A1 A2 EO GS
+     IO_STD MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     ENABLE = {CHANGED(EI,0)}
+     DATA = {CHANGED(I0,0) | CHANGED(I1,0) | CHANGED(I2,0) | CHANGED(I3,0) |
+                 CHANGED(I4,0) | CHANGED(I5,0) | CHANGED(I6,0) | CHANGED(I7,0)}
+     IN1 = {CHANGED(I1,0) & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1}
+     IN2 = {CHANGED(I2,0) & I1=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1}
+     IN3 = {CHANGED(I3,0) & I1=='1 & I2=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1}
+     IN4 = {CHANGED(I4,0) & I1=='1 & I2=='1 & I3=='1 & I5=='1 & I6=='1 & I7=='1}
+     IN5 = {CHANGED(I5,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I6=='1 & I7=='1}
+     IN6 = {CHANGED(I6,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I7=='1}
+     IN7 = {CHANGED(I7,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1}
+     IN = {IN1 | IN2 | IN3 | IN4 | IN5 | IN6 | IN7}
+
+  PINDLY:
+     A0 A1 A2 = {
+       CASE(
+         ENABLE, DELAY(-1,10ns,15ns),
+         IN & TRN_LH, DELAY(-1,10ns,15ns),
+         IN & TRN_HL, DELAY(-1,9ns,14ns),
+         TRN_LH, DELAY(-1,13ns,19ns),
+         TRN_HL, DELAY(-1,12ns,19ns),
+         DELAY(-1,14ns,20ns))}
+
+     GS = {
+       CASE(
+         ENABLE & TRN_LH, DELAY(-1,8ns,12ns),
+         ENABLE & TRN_HL, DELAY(-1,10ns,15ns),
+         DATA & TRN_LH, DELAY(-1,18ns,30ns),
+         DATA & TRN_HL, DELAY(-1,14ns,25ns),
+         DELAY(-1,19ns,31ns))}
+
+     EO = {
+       CASE(
+         ENABLE & TRN_LH, DELAY(-1,10ns,15ns),
+         ENABLE & TRN_HL, DELAY(-1,17ns,30ns),
+         DATA & TRN_LH, DELAY(-1,6ns,10ns),
+         DATA & TRN_HL, DELAY(-1,14ns,25ns),
+         DELAY(-1,18ns,31ns))}
.ENDS 74148


.SUBCKT 74F148 I0 I1 I2 I3 I4 I5 I6 I7 EI A0 A1 A2 EO GS
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(9,5) DPWR DGND
+     I0 I1 I2 I3 I4 I5 I6 I7 EI
+     A0_O A1_O A2_O EO_O GS_O
+     D0_GATE IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     i1bar = {~I1}
+     i2bar = {~I2}
+     i3bar = {~I3}
+     i4bar = {~I4}
+     i5bar = {~I5}
+     i6bar = {~I6}
+     i7bar = {~I7}
+     eibar = {~EI}
+     EO_O = {~(I0 & I1 & I2 & I3 & I4 & I5 & I6 & I7 & eibar)}
+     GS_O = {~(EO_O & eibar)}
+     A0_O = {~((i1bar & I2 & I4 & I6 & eibar) | (i3bar & I4 & I6 & eibar) | (i5bar & I6 & eibar) |
+                  (i7bar & eibar))}
+     A1_O = {~((i2bar & I4 & I5 & eibar) | (i3bar & I4 & I5 & eibar) | (i6bar & eibar) |
+                  (i7bar & eibar))}
+     A2_O = {~((i4bar & eibar) | (i5bar & eibar) | (i6bar & eibar) | (i7bar & eibar))}
U2DLY PINDLY(5,0,9) DPWR DGND
+     A0_O A1_O A2_O EO_O GS_O
+     I0 I1 I2 I3 I4 I5 I6 I7 EI
+     A0 A1 A2 EO GS
+     IO_F MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     ENABLE = {CHANGED(EI,0)}
+     DATA = {CHANGED(I0,0) | CHANGED(I1,0) | CHANGED(I2,0) | CHANGED(I3,0) |
+                 CHANGED(I4,0) | CHANGED(I5,0) | CHANGED(I6,0) | CHANGED(I7,0)}
+
+  PINDLY:
+     A0 A1 A2 = {
+       CASE(
+         ENABLE & TRN_LH, DELAY(3.5ns,6ns,8.5ns),
+         ENABLE & TRN_HL, DELAY(3ns,5.5ns,8ns),
+         DATA, DELAY(3.5ns,6ns,9ns),
+         DELAY(4.5ns,7ns,10ns))}
+
+     GS = {
+       CASE(
+         ENABLE & TRN_LH, DELAY(2.5ns,4.5ns,7ns),
+         ENABLE & TRN_HL, DELAY(3ns,5.5ns,7.5ns),
+         DATA, DELAY(2ns,4ns,8ns),
+         DELAY(4ns,6.5ns,9ns))}
+
+     EO = {
+       CASE(
+         ENABLE & TRN_LH, DELAY(3ns,5ns,7ns),
+         ENABLE & TRN_HL, DELAY(3.5ns,5ns,7.5ns),
+         DATA & TRN_LH, DELAY(1.5ns,3ns,6.5ns),
+         DATA & TRN_HL, DELAY(1.5ns,2.5ns,6.5ns),
+         DELAY(4.5ns,6ns,8.5ns))}
.ENDS 74F148


.SUBCKT 74HC148 I0 I1 I2 I3 I4 I5 I6 I7 EI A0 A1 A2 EO GS
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(9,5) DPWR DGND
+     I0 I1 I2 I3 I4 I5 I6 I7 EI
+     A0_O A1_O A2_O EO_O GS_O
+     D0_GATE IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     i1bar = {~I1}
+     i2bar = {~I2}
+     i3bar = {~I3}
+     i4bar = {~I4}
+     i5bar = {~I5}
+     i6bar = {~I6}
+     i7bar = {~I7}
+     eibar = {~EI}
+     EO_O = {~(I0 & I1 & I2 & I3 & I4 & I5 & I6 & I7 & eibar)}
+     GS_O = {~(EO_O & eibar)}
+     A0_O = {~((i1bar & I2 & I4 & I6 & eibar) | (i3bar & I4 & I6 & eibar) | (i5bar & I6 & eibar) |
+                  (i7bar & eibar))}
+     A1_O = {~((i2bar & I4 & I5 & eibar) | (i3bar & I4 & I5 & eibar) | (i6bar & eibar) |
+                  (i7bar & eibar))}
+     A2_O = {~((i4bar & eibar) | (i5bar & eibar) | (i6bar & eibar) | (i7bar & eibar))}
U2DLY PINDLY(5,0,9) DPWR DGND
+     A0_O A1_O A2_O EO_O GS_O
+     I0 I1 I2 I3 I4 I5 I6 I7 EI
+     A0 A1 A2 EO GS
+     IO_HC MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     ENABLE = {CHANGED(EI,0)}
+     DATA = {CHANGED(I0,0) | CHANGED(I1,0) | CHANGED(I2,0) | CHANGED(I3,0) |
+                 CHANGED(I4,0) | CHANGED(I5,0) | CHANGED(I6,0) | CHANGED(I7,0)}
+
+  PINDLY:
+     A0 A1 A2 = {
+       CASE(
+         ENABLE, DELAY(-1,26ns,39ns),
+         DATA, DELAY(-1,23ns,36ns),
+         DELAY(-1,27ns,40ns))}
+
+     GS = {
+       CASE(
+         ENABLE, DELAY(-1,19ns,29ns),
+         DATA, DELAY(-1,25ns,38ns),
+         DELAY(-1,26ns,39ns))}
+
+     EO = {
+       CASE(
+         ENABLE, DELAY(-1,22ns,33ns),
+         DATA, DELAY(-1,20ns,30ns),
+         DELAY(-1,23ns,34ns))}
.ENDS 74HC148


.SUBCKT 74HCT148 I0 I1 I2 I3 I4 I5 I6 I7 EI A0 A1 A2 EO GS
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(9,5) DPWR DGND
+     I0 I1 I2 I3 I4 I5 I6 I7 EI
+     A0_O A1_O A2_O EO_O GS_O
+     D0_GATE IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     i1bar = {~I1}
+     i2bar = {~I2}
+     i3bar = {~I3}
+     i4bar = {~I4}
+     i5bar = {~I5}
+     i6bar = {~I6}
+     i7bar = {~I7}
+     eibar = {~EI}
+     EO_O = {~(I0 & I1 & I2 & I3 & I4 & I5 & I6 & I7 & eibar)}
+     GS_O = {~(EO_O & eibar)}
+     A0_O = {~((i1bar & I2 & I4 & I6 & eibar) | (i3bar & I4 & I6 & eibar) | (i5bar & I6 & eibar) |
+                  (i7bar & eibar))}
+     A1_O = {~((i2bar & I4 & I5 & eibar) | (i3bar & I4 & I5 & eibar) | (i6bar & eibar) |
+                  (i7bar & eibar))}
+     A2_O = {~((i4bar & eibar) | (i5bar & eibar) | (i6bar & eibar) | (i7bar & eibar))}
U2DLY PINDLY(5,0,9) DPWR DGND
+     A0_O A1_O A2_O EO_O GS_O
+     I0 I1 I2 I3 I4 I5 I6 I7 EI
+     A0 A1 A2 EO GS
+     IO_HCT MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     ENABLE = {CHANGED(EI,0)}
+     DATA = {CHANGED(I0,0) | CHANGED(I1,0) | CHANGED(I2,0) | CHANGED(I3,0) |
+                 CHANGED(I4,0) | CHANGED(I5,0) | CHANGED(I6,0) | CHANGED(I7,0)}
+
+  PINDLY:
+     A0 A1 A2 = {
+       CASE(
+         ENABLE, DELAY(-1,16ns,28ns),
+         DATA, DELAY(-1,13ns,23ns),
+         DELAY(-1,17ns,29ns))}
+
+     GS = {
+       CASE(
+         ENABLE, DELAY(-1,11ns,21ns),
+         DATA, DELAY(-1,14ns,26ns),
+         DELAY(-1,15ns,27ns))}
+
+     EO = {
+       CASE(
+         ENABLE, DELAY(-1,13ns,23ns),
+         DATA, DELAY(-1,12ns,22ns),
+         DELAY(-1,14ns,24ns))}
.ENDS 74HCT148


.SUBCKT 74LS148 I0 I1 I2 I3 I4 I5 I6 I7 EI A0 A1 A2 EO GS
+     optional:  DPWR=$G_DPWR DGND=$G_DGND
+     params:  MNTYMXDLY=0 IO_LEVEL=0
U1LOG LOGICEXP(9,5) DPWR DGND
+     I0 I1 I2 I3 I4 I5 I6 I7 EI
+     A0_O A1_O A2_O EO_O GS_O
+     D0_GATE IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  LOGIC:
+     i1bar = {~I1}
+     i2bar = {~I2}
+     i3bar = {~I3}
+     i4bar = {~I4}
+     i5bar = {~I5}
+     i6bar = {~I6}
+     i7bar = {~I7}
+     eibar = {~EI}
+     EO_O = {~(I0 & I1 & I2 & I3 & I4 & I5 & I6 & I7 & eibar)}
+     GS_O = {~(EO_O & eibar)}
+     A0_O = {~((i1bar & I2 & I4 & I6 & eibar) | (i3bar & I4 & I6 & eibar) | (i5bar & I6 & eibar) |
+                  (i7bar & eibar))}
+     A1_O = {~((i2bar & I4 & I5 & eibar) | (i3bar & I4 & I5 & eibar) | (i6bar & eibar) |
+                  (i7bar & eibar))}
+     A2_O = {~((i4bar & eibar) | (i5bar & eibar) | (i6bar & eibar) | (i7bar & eibar))}
U2DLY PINDLY(5,0,9) DPWR DGND
+     A0_O A1_O A2_O EO_O GS_O
+     I0 I1 I2 I3 I4 I5 I6 I7 EI
+     A0 A1 A2 EO GS
+     IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}
+
+  BOOLEAN:
+     ENABLE = {CHANGED(EI,0)}
+     DATA = {CHANGED(I0,0) | CHANGED(I1,0) | CHANGED(I2,0) | CHANGED(I3,0) |
+                 CHANGED(I4,0) | CHANGED(I5,0) | CHANGED(I6,0) | CHANGED(I7,0)}
+     IN1 = {CHANGED(I1,0) & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1}
+     IN2 = {CHANGED(I2,0) & I1=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1}
+     IN3 = {CHANGED(I3,0) & I1=='1 & I2=='1 & I4=='1 & I5=='1 & I6=='1 & I7=='1}
+     IN4 = {CHANGED(I4,0) & I1=='1 & I2=='1 & I3=='1 & I5=='1 & I6=='1 & I7=='1}
+     IN5 = {CHANGED(I5,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I6=='1 & I7=='1}
+     IN6 = {CHANGED(I6,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I7=='1}
+     IN7 = {CHANGED(I7,0) & I1=='1 & I2=='1 & I3=='1 & I4=='1 & I5=='1 & I6=='1}
+     IN = {IN1 | IN2 | IN3 | IN4 | IN5 | IN6 | IN7}
+
+  PINDLY:
+     A0 A1 A2 = {
+       CASE(
+         ENABLE & TRN_LH, DELAY(-1,16ns,25ns),
+         ENABLE & TRN_HL, DELAY(-1,12ns,25ns),
+         IN & TRN_LH, DELAY(-1,14ns,18ns),
+         IN & TRN_HL, DELAY(-1,15ns,25ns),
+         TRN_LH, DELAY(-1,20ns,36ns),
+         TRN_HL, DELAY(-1,16ns,29ns),
+         DELAY(-1,21ns,37ns))}
+
+     GS = {
+       CASE(
+         ENABLE & TRN_LH, DELAY(-1,12ns,17ns),
+         ENABLE & TRN_HL, DELAY(-1,14ns,36ns),
+         DATA & TRN_LH, DELAY(-1,35ns,55ns),
+         DATA & TRN_HL, DELAY(-1,9ns,21ns),
+         DELAY(-1,36ns,56ns))}
+
+     EO = {
+       CASE(
+         ENABLE & TRN_LH, DELAY(-1,12ns,21ns),
+         ENABLE & TRN_HL, DELAY(-1,23ns,35ns),
+         DATA & TRN_LH, DELAY(-1,7ns,18ns),
+         DATA & TRN_HL, DELAY(-1,25ns,40ns),
+         DELAY(-1,26ns,41ns))}
.ENDS 74LS148


